| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 16574081
[patent_doc_number] => 10896004
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-19
[patent_title] => Data storage device and control method for non-volatile memory, with shared active block for writing commands and internal data collection
[patent_app_type] => utility
[patent_app_number] => 16/505264
[patent_app_country] => US
[patent_app_date] => 2019-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4758
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16505264
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/505264 | Data storage device and control method for non-volatile memory, with shared active block for writing commands and internal data collection | Jul 7, 2019 | Issued |
Array
(
[id] => 16494180
[patent_doc_number] => 10860221
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-08
[patent_title] => Page write to non-volatile data storage with failure recovery
[patent_app_type] => utility
[patent_app_number] => 16/503804
[patent_app_country] => US
[patent_app_date] => 2019-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 12121
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503804
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/503804 | Page write to non-volatile data storage with failure recovery | Jul 4, 2019 | Issued |
Array
(
[id] => 16551794
[patent_doc_number] => 10884954
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-05
[patent_title] => Method for performing adaptive locking range management, associated data storage device and controller thereof
[patent_app_type] => utility
[patent_app_number] => 16/503591
[patent_app_country] => US
[patent_app_date] => 2019-07-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4779
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503591
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/503591 | Method for performing adaptive locking range management, associated data storage device and controller thereof | Jul 3, 2019 | Issued |
Array
(
[id] => 15935621
[patent_doc_number] => 20200159444
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-21
[patent_title] => STORAGE DEVICE THROTTLING AMOUNT OF COMMUNICATED DATA DEPENDING ON SUSPENSION FREQUENCY OF OPERATION
[patent_app_type] => utility
[patent_app_number] => 16/428334
[patent_app_country] => US
[patent_app_date] => 2019-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12195
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16428334
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/428334 | Storage device throttling amount of communicated data depending on suspension frequency of operation | May 30, 2019 | Issued |
Array
(
[id] => 14901623
[patent_doc_number] => 20190294577
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-26
[patent_title] => ADAPTER SELECTION BASED ON A QUEUE TIME FACTOR
[patent_app_type] => utility
[patent_app_number] => 16/425229
[patent_app_country] => US
[patent_app_date] => 2019-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5265
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16425229
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/425229 | Adapter selection based on a queue time factor | May 28, 2019 | Issued |
Array
(
[id] => 14840667
[patent_doc_number] => 20190278734
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-12
[patent_title] => MULTI-MODE NMVE OVER FABRICS DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/421458
[patent_app_country] => US
[patent_app_date] => 2019-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8633
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421458
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/421458 | Multi-mode NVMe over fabrics devices | May 22, 2019 | Issued |
Array
(
[id] => 16278992
[patent_doc_number] => 10762023
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-01
[patent_title] => System architecture for supporting active pass-through board for multi-mode NMVe over fabrics devices
[patent_app_type] => utility
[patent_app_number] => 16/417248
[patent_app_country] => US
[patent_app_date] => 2019-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7356
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417248
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/417248 | System architecture for supporting active pass-through board for multi-mode NMVe over fabrics devices | May 19, 2019 | Issued |
Array
(
[id] => 15717165
[patent_doc_number] => 20200105350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-02
[patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/415695
[patent_app_country] => US
[patent_app_date] => 2019-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18208
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16415695
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/415695 | Memory controller to determine an optimal read voltage, operating method thereof and storage device including the same | May 16, 2019 | Issued |
Array
(
[id] => 16317040
[patent_doc_number] => 20200295778
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-17
[patent_title] => BIT STRING CONVERSION
[patent_app_type] => utility
[patent_app_number] => 16/415094
[patent_app_country] => US
[patent_app_date] => 2019-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18628
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16415094
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/415094 | Bit string conversion invoking bit strings having a particular data pattern | May 16, 2019 | Issued |
Array
(
[id] => 16439160
[patent_doc_number] => 20200356486
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-12
[patent_title] => SELECTIVELY HONORING SPECULATIVE MEMORY PREFETCH REQUESTS BASED ON BANDWIDTH STATE OF A MEMORY ACCESS PATH COMPONENT(S) IN A PROCESSOR-BASED SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/403701
[patent_app_country] => US
[patent_app_date] => 2019-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16549
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -38
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16403701
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/403701 | Selectively honoring speculative memory prefetch requests based on bandwidth state of a memory access path component(s) in a processor-based system | May 5, 2019 | Issued |
Array
(
[id] => 16494195
[patent_doc_number] => 10860236
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-08
[patent_title] => Method and system for proactive data migration across tiered storage
[patent_app_type] => utility
[patent_app_number] => 16/403344
[patent_app_country] => US
[patent_app_date] => 2019-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7080
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16403344
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/403344 | Method and system for proactive data migration across tiered storage | May 2, 2019 | Issued |
Array
(
[id] => 16565856
[patent_doc_number] => 10891225
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-12
[patent_title] => Host- directed sanitization of memory
[patent_app_type] => utility
[patent_app_number] => 16/402560
[patent_app_country] => US
[patent_app_date] => 2019-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4921
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402560
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/402560 | Host- directed sanitization of memory | May 2, 2019 | Issued |
Array
(
[id] => 16423885
[patent_doc_number] => 20200349083
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-05
[patent_title] => CACHE MANAGEMENT METHOD AND ASSOCIATED MICROCONTROLLER
[patent_app_type] => utility
[patent_app_number] => 16/402242
[patent_app_country] => US
[patent_app_date] => 2019-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2909
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402242
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/402242 | Cache management method using object-oriented manner and associated microcontroller | May 2, 2019 | Issued |
Array
(
[id] => 14750477
[patent_doc_number] => 20190258412
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-22
[patent_title] => PERFORMING PREPROCESSING OPERATIONS IN ANTICIPATION OF LOG FILE WRITES
[patent_app_type] => utility
[patent_app_number] => 16/399887
[patent_app_country] => US
[patent_app_date] => 2019-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7119
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399887
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/399887 | Performing preprocessing operations in anticipation of log file writes | Apr 29, 2019 | Issued |
Array
(
[id] => 16446952
[patent_doc_number] => 10838881
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-11-17
[patent_title] => Managing connections of input and output devices in a physical room
[patent_app_type] => utility
[patent_app_number] => 16/396622
[patent_app_country] => US
[patent_app_date] => 2019-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10866
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 368
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16396622
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/396622 | Managing connections of input and output devices in a physical room | Apr 25, 2019 | Issued |
Array
(
[id] => 16478345
[patent_doc_number] => 10853293
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-01
[patent_title] => Switch-based inter-device notational data movement system
[patent_app_type] => utility
[patent_app_number] => 16/396140
[patent_app_country] => US
[patent_app_date] => 2019-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8065
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16396140
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/396140 | Switch-based inter-device notational data movement system | Apr 25, 2019 | Issued |
Array
(
[id] => 15182459
[patent_doc_number] => 20190361821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-28
[patent_title] => STORAGE DEVICE INCLUDING RECONFIGURABLE LOGIC AND METHOD OF OPERATING THE STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/363791
[patent_app_country] => US
[patent_app_date] => 2019-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9515
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363791
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/363791 | Storage device including reconfigurable logic and method of operating the storage device | Mar 24, 2019 | Issued |
Array
(
[id] => 16346345
[patent_doc_number] => 20200310996
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-01
[patent_title] => Type-Based Message Bus with Message Type Hierarches for Non-Object Oriented Applications
[patent_app_type] => utility
[patent_app_number] => 16/362833
[patent_app_country] => US
[patent_app_date] => 2019-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11177
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16362833
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/362833 | Type-based message bus with message type hierarches for non-object oriented applications | Mar 24, 2019 | Issued |
Array
(
[id] => 15670751
[patent_doc_number] => 10599606
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-24
[patent_title] => 424 encoding schemes to reduce coupling and power noise on PAM-4 data buses
[patent_app_type] => utility
[patent_app_number] => 16/360212
[patent_app_country] => US
[patent_app_date] => 2019-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5662
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16360212
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/360212 | 424 encoding schemes to reduce coupling and power noise on PAM-4 data buses | Mar 20, 2019 | Issued |
Array
(
[id] => 14584933
[patent_doc_number] => 20190220075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-18
[patent_title] => UNIVERSAL SERIAL BUS POWER-DELIVERY AND SYSTEM INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/357408
[patent_app_country] => US
[patent_app_date] => 2019-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6151
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16357408
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/357408 | Method and system of universal serial bus power-delivery which stops clock signal generation until attach event occurs | Mar 18, 2019 | Issued |