Search

Burton S. Mullins

Examiner (ID: 2002, Phone: (571)272-2029 , Office: P/2834 )

Most Active Art Unit
2834
Art Unit(s)
2834, 3621, 2832, 2102
Total Applications
3052
Issued Applications
2281
Pending Applications
159
Abandoned Applications
633

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16394426 [patent_doc_number] => 20200335367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => METHOD AND SYSTEM FOR DUAL STRETCHING OF WAFERS FOR ISOLATED SEGMENTED CHIP SCALE PACKAGES [patent_app_type] => utility [patent_app_number] => 16/868268 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868268 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/868268
Method and system for dual stretching of wafers for isolated segmented chip scale packages May 5, 2020 Issued
Array ( [id] => 16180580 [patent_doc_number] => 20200227549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS THEREFOR [patent_app_type] => utility [patent_app_number] => 16/816463 [patent_app_country] => US [patent_app_date] => 2020-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16816463 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/816463
Semiconductor device and manufacturing process therefor Mar 11, 2020 Issued
Array ( [id] => 16609462 [patent_doc_number] => 10910478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Metal-oxide-semiconductor field-effect transistor having enhanced high-frequency performance [patent_app_type] => utility [patent_app_number] => 16/808703 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 38 [patent_no_of_words] => 12461 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808703 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/808703
Metal-oxide-semiconductor field-effect transistor having enhanced high-frequency performance Mar 3, 2020 Issued
Array ( [id] => 16433104 [patent_doc_number] => 10833203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Transistor and semiconductor device [patent_app_type] => utility [patent_app_number] => 16/789474 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 46 [patent_no_of_words] => 24962 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16789474 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/789474
Transistor and semiconductor device Feb 12, 2020 Issued
Array ( [id] => 16668640 [patent_doc_number] => 10937899 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-02 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/785007 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 4740 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785007 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/785007
Semiconductor device Feb 6, 2020 Issued
Array ( [id] => 16001103 [patent_doc_number] => 20200176422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => METHOD AND DEVICE FOR CONTROLLING OPERATION USING TEMPERATURE DEVIATION IN MULTI-CHIP PACKAGE [patent_app_type] => utility [patent_app_number] => 16/782267 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16782267 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/782267
Method and device for controlling operation using temperature deviation in multi-chip package Feb 4, 2020 Issued
Array ( [id] => 16163235 [patent_doc_number] => 20200219850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => Methods and Systems for Wafer Bonding Alignment Compensation [patent_app_type] => utility [patent_app_number] => 16/736689 [patent_app_country] => US [patent_app_date] => 2020-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16736689 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/736689
Methods and systems for wafer bonding alignment compensation Jan 6, 2020 Issued
Array ( [id] => 16386473 [patent_doc_number] => 10811318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => FIN field effect transistor (FinFET) device structure with dummy FIN structure [patent_app_type] => utility [patent_app_number] => 16/730320 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 6436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730320 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730320
FIN field effect transistor (FinFET) device structure with dummy FIN structure Dec 29, 2019 Issued
Array ( [id] => 16249534 [patent_doc_number] => 10748909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Methods of fabricating semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/711833 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 6228 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16711833 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/711833
Methods of fabricating semiconductor devices Dec 11, 2019 Issued
Array ( [id] => 16684502 [patent_doc_number] => 10943994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Manufacturing method for shielded gate trench device [patent_app_type] => utility [patent_app_number] => 16/705701 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 5537 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705701 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/705701
Manufacturing method for shielded gate trench device Dec 5, 2019 Issued
Array ( [id] => 15776335 [patent_doc_number] => 20200119185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => MOS DEVICE WITH ISLAND REGION [patent_app_type] => utility [patent_app_number] => 16/705029 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705029 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/705029
MOS device with island region Dec 4, 2019 Issued
Array ( [id] => 16218578 [patent_doc_number] => 10734401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-04 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/681624 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6576 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681624 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681624
Semiconductor memory device Nov 11, 2019 Issued
Array ( [id] => 16521718 [patent_doc_number] => 10872944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Display substrate, method of manufacturing display substrate, and display device including display substrate [patent_app_type] => utility [patent_app_number] => 16/681697 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8892 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681697 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681697
Display substrate, method of manufacturing display substrate, and display device including display substrate Nov 11, 2019 Issued
Array ( [id] => 15969947 [patent_doc_number] => 20200168725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/681640 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681640
Semiconductor device Nov 11, 2019 Issued
Array ( [id] => 16593960 [patent_doc_number] => 10903237 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-26 [patent_title] => Three-dimensional memory device including stepped connection plates and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/671561 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 80 [patent_no_of_words] => 24702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671561 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671561
Three-dimensional memory device including stepped connection plates and methods of forming the same Oct 31, 2019 Issued
Array ( [id] => 16386608 [patent_doc_number] => 10811453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => Pillar structures for suppressing optical cross-talk [patent_app_type] => utility [patent_app_number] => 16/671608 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 7284 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671608 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671608
Pillar structures for suppressing optical cross-talk Oct 31, 2019 Issued
Array ( [id] => 16448412 [patent_doc_number] => 10840343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Semiconductor structure for wide bandgap normally off MOSFET [patent_app_type] => utility [patent_app_number] => 16/671549 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3135 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671549 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671549
Semiconductor structure for wide bandgap normally off MOSFET Oct 31, 2019 Issued
Array ( [id] => 15564293 [patent_doc_number] => 20200066558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => METHOD AND SYSTEM FOR DUAL STRETCHING OF WAFERS FOR ISOLATED SEGMENTED CHIP SCALE PACKAGES [patent_app_type] => utility [patent_app_number] => 16/670503 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670503 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670503
Method and system for dual stretching of wafers for isolated segmented chip scale packages Oct 30, 2019 Issued
Array ( [id] => 16739037 [patent_doc_number] => 10964703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/663278 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 45 [patent_no_of_words] => 7257 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16663278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/663278
Semiconductor device and method for fabricating the same Oct 23, 2019 Issued
Array ( [id] => 16593959 [patent_doc_number] => 10903236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Three-dimensional semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/663228 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 12982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16663228 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/663228
Three-dimensional semiconductor memory device Oct 23, 2019 Issued
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