Byron S. Everhart

Array ( [id] => 2708235 [patent_doc_number] => 05017511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-21 [patent_title] => 'Method for dry etching vias in integrated circuit layers' [patent_app_type] => 1 [patent_app_number] => 7/377514 [patent_app_country] => US [patent_app_date] => 1989-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3600 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/017/05017511.pdf [firstpage_image] =>[orig_patent_app_number] => 377514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2747572 [patent_doc_number] => 05037782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-06 [patent_title] => 'Method of making a semiconductor device including via holes' [patent_app_type] => 1 [patent_app_number] => 7/376014 [patent_app_country] => US [patent_app_date] => 1989-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1311 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/037/05037782.pdf [firstpage_image] =>[orig_patent_app_number] => 376014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2742678 [patent_doc_number] => 05023203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-11 [patent_title] => 'Method of patterning fine line width semiconductor topology using a spacer' [patent_app_type] => 1 [patent_app_number] => 7/370872 [patent_app_country] => US [patent_app_date] => 1989-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 38 [patent_no_of_words] => 2716 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/023/05023203.pdf [firstpage_image] =>[orig_patent_app_number] => 370872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2866547 [patent_doc_number] => 05096854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-17 [patent_title] => 'Method for polishing a silicon wafer using a ceramic polishing surface having a maximum surface roughness less than 0.02 microns' [patent_app_type] => 1 [patent_app_number] => 7/367637 [patent_app_country] => US [patent_app_date] => 1989-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 4116 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/096/05096854.pdf [firstpage_image] =>[orig_patent_app_number] => 367637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2584876 [patent_doc_number] => 04925813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-15 [patent_title] => 'Method of manufacturing semiconductor devices including at least a reactive ion etching step' [patent_app_type] => 1 [patent_app_number] => 7/366107 [patent_app_country] => US [patent_app_date] => 1989-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2690 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/925/04925813.pdf [firstpage_image] =>[orig_patent_app_number] => 366107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2625774 [patent_doc_number] => 04920078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-24 [patent_title] => 'Arsenic sulfide surface passivation of III-V semiconductors' [patent_app_type] => 1 [patent_app_number] => 7/360414 [patent_app_country] => US [patent_app_date] => 1989-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2853 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/920/04920078.pdf [firstpage_image] =>[orig_patent_app_number] => 360414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2698113 [patent_doc_number] => 04988644 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-29 [patent_title] => 'Method for etching semiconductor materials using a remote plasma generator' [patent_app_type] => 1 [patent_app_number] => 7/355942 [patent_app_country] => US [patent_app_date] => 1989-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3866 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/988/04988644.pdf [firstpage_image] =>[orig_patent_app_number] => 355942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2624160 [patent_doc_number] => 04950616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-21 [patent_title] => 'Method for fabricating a BiCMOS device' [patent_app_type] => 1 [patent_app_number] => 7/353105 [patent_app_country] => US [patent_app_date] => 1989-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1374 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/950/04950616.pdf [firstpage_image] =>[orig_patent_app_number] => 353105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2743298 [patent_doc_number] => 05011794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-30 [patent_title] => 'Procedure for rapid thermal annealing of implanted semiconductors' [patent_app_type] => 1 [patent_app_number] => 7/345923 [patent_app_country] => US [patent_app_date] => 1989-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4703 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/011/05011794.pdf [firstpage_image] =>[orig_patent_app_number] => 345923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2772668 [patent_doc_number] => 05132252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'Method for fabricating semiconductor devices that prevents pattern contamination' [patent_app_type] => 1 [patent_app_number] => 7/343456 [patent_app_country] => US [patent_app_date] => 1989-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 4503 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132252.pdf [firstpage_image] =>[orig_patent_app_number] => 343456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3489063 [patent_doc_number] => 05470799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Method for pretreating semiconductor substrate by photochemically removing native oxide' [patent_app_type] => 1 [patent_app_number] => 7/342045 [patent_app_country] => US [patent_app_date] => 1989-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6532 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/470/05470799.pdf [firstpage_image] =>[orig_patent_app_number] => 342045 [rel_patent_id] =>[rel_patent_doc_number] =>)