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Byron S. Everhart

Examiner (ID: 12669)

Most Active Art Unit
1104
Art Unit(s)
1104, 1109
Total Applications
352
Issued Applications
236
Pending Applications
3
Abandoned Applications
113

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2624198 [patent_doc_number] => 04950618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-21 [patent_title] => 'Masking scheme for silicon dioxide mesa formation' [patent_app_type] => 1 [patent_app_number] => 7/338719 [patent_app_country] => US [patent_app_date] => 1989-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 2498 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/950/04950618.pdf [firstpage_image] =>[orig_patent_app_number] => 338719 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/338719
Masking scheme for silicon dioxide mesa formation Apr 13, 1989 Issued
Array ( [id] => 2656342 [patent_doc_number] => 04962049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-09 [patent_title] => 'Process for the plasma treatment of the backside of a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 7/337607 [patent_app_country] => US [patent_app_date] => 1989-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/962/04962049.pdf [firstpage_image] =>[orig_patent_app_number] => 337607 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/337607
Process for the plasma treatment of the backside of a semiconductor wafer Apr 12, 1989 Issued
07/335626 DEVICE FABRICATION AND RESULTING DEVICES Apr 9, 1989 Abandoned
Array ( [id] => 3094113 [patent_doc_number] => 05298466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Method and apparatus for dry anisotropically etching a substrate' [patent_app_type] => 1 [patent_app_number] => 7/348664 [patent_app_country] => US [patent_app_date] => 1989-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1640 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/298/05298466.pdf [firstpage_image] =>[orig_patent_app_number] => 348664 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/348664
Method and apparatus for dry anisotropically etching a substrate Apr 5, 1989 Issued
07/330269 METHOD FOR THE MANUFACTURE OF BORON-CONTAINING FILMS Mar 28, 1989 Abandoned
Array ( [id] => 3000295 [patent_doc_number] => 05354386 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Method for plasma etching tapered and stepped vias' [patent_app_type] => 1 [patent_app_number] => 7/328179 [patent_app_country] => US [patent_app_date] => 1989-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4641 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/354/05354386.pdf [firstpage_image] =>[orig_patent_app_number] => 328179 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/328179
Method for plasma etching tapered and stepped vias Mar 23, 1989 Issued
Array ( [id] => 2857396 [patent_doc_number] => 05084419 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-28 [patent_title] => 'Method of manufacturing semiconductor device using chemical-mechanical polishing' [patent_app_type] => 1 [patent_app_number] => 7/327602 [patent_app_country] => US [patent_app_date] => 1989-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3478 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/084/05084419.pdf [firstpage_image] =>[orig_patent_app_number] => 327602 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/327602
Method of manufacturing semiconductor device using chemical-mechanical polishing Mar 22, 1989 Issued
Array ( [id] => 2645057 [patent_doc_number] => 04980317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-25 [patent_title] => 'Method of producing integrated semiconductor structures comprising field-effect transistors with channel lengths in the submicron range using a three-layer resist system' [patent_app_type] => 1 [patent_app_number] => 7/326352 [patent_app_country] => US [patent_app_date] => 1989-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 3322 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/980/04980317.pdf [firstpage_image] =>[orig_patent_app_number] => 326352 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/326352
Method of producing integrated semiconductor structures comprising field-effect transistors with channel lengths in the submicron range using a three-layer resist system Mar 20, 1989 Issued
07/326831 AMORPHOUS SEMICONDUCTOR, AMORPHOUS SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME Mar 20, 1989 Abandoned
Array ( [id] => 2626314 [patent_doc_number] => 04906592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-06 [patent_title] => 'Method for forming a multilayered metal network for bonding components of a high-density integrated circuit using a spin on glass layer' [patent_app_type] => 1 [patent_app_number] => 7/323049 [patent_app_country] => US [patent_app_date] => 1989-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2262 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/906/04906592.pdf [firstpage_image] =>[orig_patent_app_number] => 323049 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/323049
Method for forming a multilayered metal network for bonding components of a high-density integrated circuit using a spin on glass layer Mar 13, 1989 Issued
Array ( [id] => 2747726 [patent_doc_number] => 05021365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-04 [patent_title] => 'Compound semiconductor interface control using cationic ingredient oxide to prevent fermi level pinning' [patent_app_type] => 1 [patent_app_number] => 7/322583 [patent_app_country] => US [patent_app_date] => 1989-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3648 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/021/05021365.pdf [firstpage_image] =>[orig_patent_app_number] => 322583 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/322583
Compound semiconductor interface control using cationic ingredient oxide to prevent fermi level pinning Mar 12, 1989 Issued
Array ( [id] => 2706076 [patent_doc_number] => 04981815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-01 [patent_title] => 'Method for rapidly thermally processing a semiconductor wafer by irradiation using semicircular or parabolic reflectors' [patent_app_type] => 1 [patent_app_number] => 7/322113 [patent_app_country] => US [patent_app_date] => 1989-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3032 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/981/04981815.pdf [firstpage_image] =>[orig_patent_app_number] => 322113 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/322113
Method for rapidly thermally processing a semiconductor wafer by irradiation using semicircular or parabolic reflectors Mar 12, 1989 Issued
07/318209 PRODUCING METHOD OF SEMICONDUCTOR DEVICE AND FILM FORMING APPARATUS USED THEREFOR Mar 2, 1989 Abandoned
Array ( [id] => 2999422 [patent_doc_number] => 05374318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-20 [patent_title] => 'Process for the deposition of diamond films using low energy, mass-selected ion beam deposition' [patent_app_type] => 1 [patent_app_number] => 7/348727 [patent_app_country] => US [patent_app_date] => 1989-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 16868 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/374/05374318.pdf [firstpage_image] =>[orig_patent_app_number] => 348727 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/348727
Process for the deposition of diamond films using low energy, mass-selected ion beam deposition Feb 23, 1989 Issued
07/311326 PROCESS FOR THE VAPOR DEPOSITION OF POLYSILANES Feb 14, 1989 Abandoned
07/310287 GETTERING TREATMENT PROCESS Feb 13, 1989 Abandoned
07/309515 COMPLEMENTARY BIPOLAR AND MOS TRANSISTOR HAVING POWER AND LOGIC STRUCTURES ON THE SAME INTEGRATED CIRCUIT SUBSTRATE Feb 9, 1989 Abandoned
07/303754 METHOD OF FORMING CURRENT BARRIERS IN SEMICONDUCTOR LASERS Jan 26, 1989 Abandoned
Array ( [id] => 2761746 [patent_doc_number] => 04994400 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-19 [patent_title] => 'Method of fabricating a semiconductor device using a tri-layer structure and conductive sidewalls' [patent_app_type] => 1 [patent_app_number] => 7/302519 [patent_app_country] => US [patent_app_date] => 1989-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3744 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/994/04994400.pdf [firstpage_image] =>[orig_patent_app_number] => 302519 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/302519
Method of fabricating a semiconductor device using a tri-layer structure and conductive sidewalls Jan 26, 1989 Issued
Array ( [id] => 2555388 [patent_doc_number] => 04897366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-30 [patent_title] => 'Method of making silicon-on-insulator islands' [patent_app_type] => 1 [patent_app_number] => 7/298148 [patent_app_country] => US [patent_app_date] => 1989-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1095 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/897/04897366.pdf [firstpage_image] =>[orig_patent_app_number] => 298148 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/298148
Method of making silicon-on-insulator islands Jan 17, 1989 Issued
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