Search

Caleb E. Henry

Examiner (ID: 13871, Phone: (571)270-5370 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2818, 2894
Total Applications
1607
Issued Applications
1337
Pending Applications
112
Abandoned Applications
182

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11990246 [patent_doc_number] => 20170294401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/477170 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477170 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477170
Semiconductor packages and methods for forming semiconductor package Apr 2, 2017 Issued
Array ( [id] => 13769717 [patent_doc_number] => 10177208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Flexible display apparatus including a curved surface portion having a correcting layer [patent_app_type] => utility [patent_app_number] => 15/470171 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5742 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470171 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/470171
Flexible display apparatus including a curved surface portion having a correcting layer Mar 26, 2017 Issued
Array ( [id] => 12314202 [patent_doc_number] => 09941119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Method of forming silicon layer in manufacturing semiconductor device and recording medium [patent_app_type] => utility [patent_app_number] => 15/468966 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 48 [patent_no_of_words] => 22867 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15468966 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/468966
Method of forming silicon layer in manufacturing semiconductor device and recording medium Mar 23, 2017 Issued
Array ( [id] => 16372731 [patent_doc_number] => 10804497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Organic optoelectronic component with a coupling-out layer [patent_app_type] => utility [patent_app_number] => 16/087306 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5393 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16087306 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/087306
Organic optoelectronic component with a coupling-out layer Mar 19, 2017 Issued
Array ( [id] => 11967270 [patent_doc_number] => 20170271424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'THIN FILM TRANSISTOR SUBSTRATE, AN ORGANIC LIGHT-EMITTING DISPLAY APPARATUS USING THE SAME, AND A METHOD OF MANUFACTURING THE THIN FILM TRANSISTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/461772 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15461772 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/461772
Thin film transistor substrate, an organic light-emitting display apparatus using the same, and a method of manufacturing the thin film transistor substrate Mar 16, 2017 Issued
Array ( [id] => 13243309 [patent_doc_number] => 10134866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Field effect transistor air-gap spacers with an etch-stop layer [patent_app_type] => utility [patent_app_number] => 15/459224 [patent_app_country] => US [patent_app_date] => 2017-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6192 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15459224 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/459224
Field effect transistor air-gap spacers with an etch-stop layer Mar 14, 2017 Issued
Array ( [id] => 11967271 [patent_doc_number] => 20170271423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/459257 [patent_app_country] => US [patent_app_date] => 2017-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15459257 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/459257
Display device having multiple protective films Mar 14, 2017 Issued
Array ( [id] => 14177831 [patent_doc_number] => 10262936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/459255 [patent_app_country] => US [patent_app_date] => 2017-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 2976 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15459255 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/459255
Semiconductor device and manufacturing method thereof Mar 14, 2017 Issued
Array ( [id] => 14205559 [patent_doc_number] => 10269906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Semiconductor device having two spacers [patent_app_type] => utility [patent_app_number] => 15/459155 [patent_app_country] => US [patent_app_date] => 2017-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 36 [patent_no_of_words] => 5555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15459155 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/459155
Semiconductor device having two spacers Mar 14, 2017 Issued
Array ( [id] => 11710797 [patent_doc_number] => 20170179296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'MANUFACTURE METHOD OF DUAL GATE OXIDE SEMICONDUCTOR TFT SUBSTRATE AND STRUCTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 15/455082 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6640 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15455082 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/455082
Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof Mar 8, 2017 Issued
Array ( [id] => 11952303 [patent_doc_number] => 20170256454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'WAFER PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 15/450828 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5287 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450828 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450828
Wafer processing method Mar 5, 2017 Issued
Array ( [id] => 11974553 [patent_doc_number] => 20170278707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'RADIAL AND THICKNESS CONTROL VIA BIASED MULTI-PORT INJECTION SETTINGS' [patent_app_type] => utility [patent_app_number] => 15/450199 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3371 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450199 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450199
Radial and thickness control via biased multi-port injection settings Mar 5, 2017 Issued
Array ( [id] => 12416631 [patent_doc_number] => 09972490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Plasma stabilization method and deposition method using the same [patent_app_type] => utility [patent_app_number] => 15/451273 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15451273 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/451273
Plasma stabilization method and deposition method using the same Mar 5, 2017 Issued
Array ( [id] => 12416700 [patent_doc_number] => 09972513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Device and method for treating a substrate with hydrofluoric and nitric acid [patent_app_type] => utility [patent_app_number] => 15/450542 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3832 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450542 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450542
Device and method for treating a substrate with hydrofluoric and nitric acid Mar 5, 2017 Issued
Array ( [id] => 11952299 [patent_doc_number] => 20170256450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'RECESS FILLING METHOD AND PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/450595 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5823 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450595 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450595
Recess filling method and processing apparatus Mar 5, 2017 Issued
Array ( [id] => 12250211 [patent_doc_number] => 09922995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Structure of dual gate oxide semiconductor TFT substrate including TFT having top and bottom gates' [patent_app_type] => utility [patent_app_number] => 15/390734 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5008 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 421 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390734 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/390734
Structure of dual gate oxide semiconductor TFT substrate including TFT having top and bottom gates Dec 26, 2016 Issued
Array ( [id] => 14603735 [patent_doc_number] => 10355065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Double-sided display and method of packaging the same [patent_app_type] => utility [patent_app_number] => 15/322747 [patent_app_country] => US [patent_app_date] => 2016-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5152 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15322747 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/322747
Double-sided display and method of packaging the same Dec 22, 2016 Issued
Array ( [id] => 11557842 [patent_doc_number] => 20170104088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'METHOD AND APPARATUS FOR SOURCE-DRAIN JUNCTION FORMATION IN A FINFET WITH IN-SITU DOPING' [patent_app_type] => utility [patent_app_number] => 15/385811 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9960 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385811 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385811
METHOD AND APPARATUS FOR SOURCE-DRAIN JUNCTION FORMATION IN A FINFET WITH IN-SITU DOPING Dec 19, 2016 Abandoned
Array ( [id] => 12553980 [patent_doc_number] => 10014217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Method of singulating semiconductor wafer having a plurality of die and a back layer disposed along a major surface [patent_app_type] => utility [patent_app_number] => 15/384646 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 7639 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384646 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/384646
Method of singulating semiconductor wafer having a plurality of die and a back layer disposed along a major surface Dec 19, 2016 Issued
Array ( [id] => 11532522 [patent_doc_number] => 20170092499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'ELECTROLESS PLATING SOLUTION WITH AT LEAST TWO BORANE CONTAINING REDUCING AGENTS' [patent_app_type] => utility [patent_app_number] => 15/372785 [patent_app_country] => US [patent_app_date] => 2016-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2077 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15372785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/372785
Method of electroless plating using a solution with at least two borane containing reducing agents Dec 7, 2016 Issued
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