Search

Caleb E. Henry

Examiner (ID: 13871, Phone: (571)270-5370 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2818, 2894
Total Applications
1607
Issued Applications
1337
Pending Applications
112
Abandoned Applications
182

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10758586 [patent_doc_number] => 20160104738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-14 [patent_title] => 'IMAGE SENSING DEVICE WITH INTERCONNECT LAYER GAP AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 14/741561 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2290 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741561 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741561
Image sensing device with interconnect layer gap Jun 16, 2015 Issued
Array ( [id] => 10718266 [patent_doc_number] => 20160064413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/742107 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6066 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742107 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742107
Array substrate, method for manufacturing the same and display device Jun 16, 2015 Issued
Array ( [id] => 11891152 [patent_doc_number] => 09761719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Semiconductor device having silicon-germanium source/drain regions with varying germanium concentrations' [patent_app_type] => utility [patent_app_number] => 14/741454 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 39 [patent_no_of_words] => 13318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741454 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741454
Semiconductor device having silicon-germanium source/drain regions with varying germanium concentrations Jun 16, 2015 Issued
Array ( [id] => 10402643 [patent_doc_number] => 20150287652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'Calculating Carrier Concentrations in Semiconductor Fins Using Probed Resistance' [patent_app_type] => utility [patent_app_number] => 14/742439 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742439 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742439
Methods for probing semiconductor fins and determining carrier concentrations therein Jun 16, 2015 Issued
Array ( [id] => 10697034 [patent_doc_number] => 20160043181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'ELECTRONIC DEVICE INCLUDING A CHANNEL LAYER INCLUDING A COMPOUND SEMICONDUCTOR MATERIAL' [patent_app_type] => utility [patent_app_number] => 14/741567 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741567 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741567
Electronic device including a channel layer including gallium nitride Jun 16, 2015 Issued
Array ( [id] => 10487126 [patent_doc_number] => 20150372146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'SEMICONDUCTOR DEVICE AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/741961 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 40354 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741961 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741961
Semiconductor device including first gate oxide semiconductor film, and second gate Jun 16, 2015 Issued
Array ( [id] => 10479439 [patent_doc_number] => 20150364457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'Wafer Leveled Chip Packaging Structure and Method Thereof' [patent_app_type] => utility [patent_app_number] => 14/740184 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4882 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14740184 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/740184
Electrically stackable semiconductor wafer and chip packages Jun 14, 2015 Issued
Array ( [id] => 10631830 [patent_doc_number] => 09349987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-24 [patent_title] => 'Method of manufacturing OLED display apparatus' [patent_app_type] => utility [patent_app_number] => 14/739716 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4458 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14739716 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/739716
Method of manufacturing OLED display apparatus Jun 14, 2015 Issued
Array ( [id] => 10426305 [patent_doc_number] => 20150311316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'VARIABLE RESISTIVE MEMORY DEVICE INCLUDING VERTICAL CHANNEL PMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/737239 [patent_app_country] => US [patent_app_date] => 2015-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3090 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14737239 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/737239
Variable resistive memory device including vertical channel PMOS transistor and method of manufacturing the same Jun 10, 2015 Issued
Array ( [id] => 10479304 [patent_doc_number] => 20150364321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'Alkyl-Alkoxysilacyclic Compounds and Methods for Depositing Films Using Same' [patent_app_type] => utility [patent_app_number] => 14/732250 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 11470 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732250 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732250
Alkyl-alkoxysilacyclic compounds Jun 4, 2015 Issued
Array ( [id] => 11802350 [patent_doc_number] => 09543250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Semiconductor devices including through-silicon via' [patent_app_type] => utility [patent_app_number] => 14/729264 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8368 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14729264 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/729264
Semiconductor devices including through-silicon via Jun 2, 2015 Issued
Array ( [id] => 11578990 [patent_doc_number] => 09634260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Method for preparing conjugated compound having phenoxathiin and electron donating group of conjugated aromatic unit, and OLED device having the conjugated compound' [patent_app_type] => utility [patent_app_number] => 14/763827 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7363 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14763827 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/763827
Method for preparing conjugated compound having phenoxathiin and electron donating group of conjugated aromatic unit, and OLED device having the conjugated compound May 21, 2015 Issued
Array ( [id] => 11125592 [patent_doc_number] => 20160322567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'CONJUGATED COMPOUND CONTAINING BIS(PHENYLSULFONYL)BENZENE STRUCTURE, PREPARATION METHOD AND APPLICATION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/763830 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6951 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14763830 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/763830
Preparation method of conjugated compound containing bis(phenylsulfonyl)benzene structure and an organic electroluminescent diode device using the conjugated compound May 21, 2015 Issued
Array ( [id] => 11898262 [patent_doc_number] => 09768203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'TFT arrangement structure comprising stacked dual TFT\'s' [patent_app_type] => utility [patent_app_number] => 14/770089 [patent_app_country] => US [patent_app_date] => 2015-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3857 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 479 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14770089 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/770089
TFT arrangement structure comprising stacked dual TFT's May 21, 2015 Issued
Array ( [id] => 11110962 [patent_doc_number] => 20160307932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'MANUFACTURE METHOD OF DUAL GATE OXIDE SEMICONDUCTOR TFT SUBSTRATE AND STRUCTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 14/763822 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6580 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14763822 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/763822
Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof May 20, 2015 Issued
Array ( [id] => 10624614 [patent_doc_number] => 09343564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Semiconductor device including a gate electrode on a protruding group III-V material layer and method of manufacturing the semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/718968 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3901 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14718968 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/718968
Semiconductor device including a gate electrode on a protruding group III-V material layer and method of manufacturing the semiconductor device May 20, 2015 Issued
Array ( [id] => 11802537 [patent_doc_number] => 09543442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof' [patent_app_type] => utility [patent_app_number] => 14/763823 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4550 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 555 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14763823 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/763823
Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof May 20, 2015 Issued
Array ( [id] => 11293940 [patent_doc_number] => 20160343872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'MANUFACTURE METHOD OF DUAL GATE OXIDE SEMICONDUCTOR TFT SUBSTRATE AND STRUCTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 14/763824 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4949 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14763824 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/763824
Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof May 20, 2015 Issued
Array ( [id] => 11000327 [patent_doc_number] => 20160197274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/891091 [patent_app_country] => US [patent_app_date] => 2015-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4394 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14891091 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/891091
Thin film transistor having germanium thin film and manufacturing method thereof, array substrate, display device May 13, 2015 Issued
Array ( [id] => 11360378 [patent_doc_number] => 09537037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Wet etching method for an N-type bifacial cell' [patent_app_type] => utility [patent_app_number] => 15/028665 [patent_app_country] => US [patent_app_date] => 2015-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7042 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15028665 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/028665
Wet etching method for an N-type bifacial cell May 13, 2015 Issued
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