Search

Caleb E. Henry

Examiner (ID: 13871, Phone: (571)270-5370 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2818, 2894
Total Applications
1607
Issued Applications
1337
Pending Applications
112
Abandoned Applications
182

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10179176 [patent_doc_number] => 09209391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Electronic memory device having an electrode made of a soluble material' [patent_app_type] => utility [patent_app_number] => 14/091623 [patent_app_country] => US [patent_app_date] => 2013-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 6810 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14091623 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/091623
Electronic memory device having an electrode made of a soluble material Nov 26, 2013 Issued
Array ( [id] => 10016372 [patent_doc_number] => 09059395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Resistive random access memory devices having variable resistance layers and related methods' [patent_app_type] => utility [patent_app_number] => 14/090803 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 60 [patent_no_of_words] => 14961 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090803 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/090803
Resistive random access memory devices having variable resistance layers and related methods Nov 25, 2013 Issued
Array ( [id] => 10093232 [patent_doc_number] => 09130064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Method for fabricating leadframe-based semiconductor package with connecting pads top and bottom surfaces of carrier' [patent_app_type] => utility [patent_app_number] => 14/086142 [patent_app_country] => US [patent_app_date] => 2013-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5096 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086142 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/086142
Method for fabricating leadframe-based semiconductor package with connecting pads top and bottom surfaces of carrier Nov 20, 2013 Issued
Array ( [id] => 9951021 [patent_doc_number] => 08999808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Nonvolatile memory element and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/082237 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 15000 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082237 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082237
Nonvolatile memory element and method for manufacturing the same Nov 17, 2013 Issued
Array ( [id] => 10740940 [patent_doc_number] => 20160087091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'INSULATING GATE FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/787545 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7421 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14787545 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/787545
Transistor and switching system comprising silicon carbide and oxides of varying thicknesses, and method for providing the same Nov 17, 2013 Issued
Array ( [id] => 10016160 [patent_doc_number] => 09059181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Wafer leveled chip packaging structure and method thereof' [patent_app_type] => utility [patent_app_number] => 14/083377 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4851 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083377 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/083377
Wafer leveled chip packaging structure and method thereof Nov 17, 2013 Issued
Array ( [id] => 10870149 [patent_doc_number] => 08895344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Method of making a low stress cavity package for back side illuminated image sensor' [patent_app_type] => utility [patent_app_number] => 14/079751 [patent_app_country] => US [patent_app_date] => 2013-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3253 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14079751 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/079751
Method of making a low stress cavity package for back side illuminated image sensor Nov 13, 2013 Issued
Array ( [id] => 10850951 [patent_doc_number] => 08877630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-04 [patent_title] => 'Semiconductor structure having a silver alloy bump body and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/078240 [patent_app_country] => US [patent_app_date] => 2013-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 15236 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14078240 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/078240
Semiconductor structure having a silver alloy bump body and manufacturing method thereof Nov 11, 2013 Issued
Array ( [id] => 10041984 [patent_doc_number] => 09082697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'Variable resistive memory device including vertical channel PMOS transistor and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/076921 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3090 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076921 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/076921
Variable resistive memory device including vertical channel PMOS transistor and method of manufacturing the same Nov 10, 2013 Issued
Array ( [id] => 9671136 [patent_doc_number] => 20140234999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'METHOD FOR PROCESSING DEVICES INCLUDING QUANTUM DOTS AND DEVICES' [patent_app_type] => utility [patent_app_number] => 14/076409 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 16416 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076409 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/076409
Method for processing devices including quantum dots and devices Nov 10, 2013 Issued
Array ( [id] => 10172072 [patent_doc_number] => 09202785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Three dimensional integrated circuit capacitor having vias' [patent_app_type] => utility [patent_app_number] => 14/074972 [patent_app_country] => US [patent_app_date] => 2013-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074972 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/074972
Three dimensional integrated circuit capacitor having vias Nov 7, 2013 Issued
Array ( [id] => 9844753 [patent_doc_number] => 08946670 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-03 [patent_title] => 'Three-dimensional semiconductor device, variable resistive memory device including the same, and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/075910 [patent_app_country] => US [patent_app_date] => 2013-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3076 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14075910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/075910
Three-dimensional semiconductor device, variable resistive memory device including the same, and method of manufacturing the same Nov 7, 2013 Issued
Array ( [id] => 10245031 [patent_doc_number] => 20150130026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'PRINTING MINIMUM WIDTH FEATURES AT NON-MINIMUM PITCH AND RESULTING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/074981 [patent_app_country] => US [patent_app_date] => 2013-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074981 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/074981
Printing minimum width semiconductor features at non-minimum pitch and resulting device Nov 7, 2013 Issued
Array ( [id] => 10010508 [patent_doc_number] => 09054033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Semiconductor device having vertical channel, resistive memory device including the same, and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/074404 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5707 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074404 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/074404
Semiconductor device having vertical channel, resistive memory device including the same, and method of manufacturing the same Nov 6, 2013 Issued
Array ( [id] => 10158614 [patent_doc_number] => 09190398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Method for packaging an optical module' [patent_app_type] => utility [patent_app_number] => 14/073567 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1717 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14073567 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/073567
Method for packaging an optical module Nov 5, 2013 Issued
Array ( [id] => 9728533 [patent_doc_number] => 20140264241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'ZnTe on TiN or Pt Electrodes as a Resistive Switching Element for ReRAM Applications' [patent_app_type] => utility [patent_app_number] => 14/073718 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14073718 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/073718
ZnTe on TiN or Pt electodes with a portion operable as a current limiting layer for ReRAM applications Nov 5, 2013 Issued
Array ( [id] => 10053680 [patent_doc_number] => 09093567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Diodes with multiple junctions and fabrication methods therefor' [patent_app_type] => utility [patent_app_number] => 14/072151 [patent_app_country] => US [patent_app_date] => 2013-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8909 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14072151 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/072151
Diodes with multiple junctions and fabrication methods therefor Nov 4, 2013 Issued
Array ( [id] => 10238152 [patent_doc_number] => 20150123146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'INCREASED SPACE BETWEEN EPITAXY ON ADJACENT FINS OF FINFET' [patent_app_type] => utility [patent_app_number] => 14/071170 [patent_app_country] => US [patent_app_date] => 2013-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14071170 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/071170
Semiconductor structure with increased space and volume between shaped epitaxial structures Nov 3, 2013 Issued
Array ( [id] => 9923367 [patent_doc_number] => 08981334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-17 [patent_title] => 'Memory cells having regions containing one or both of carbon and boron' [patent_app_type] => utility [patent_app_number] => 14/070407 [patent_app_country] => US [patent_app_date] => 2013-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3658 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14070407 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/070407
Memory cells having regions containing one or both of carbon and boron Oct 31, 2013 Issued
Array ( [id] => 10230335 [patent_doc_number] => 20150115329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'Method and Apparatus for Repairing Monolithic Stacked Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 14/068187 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5518 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14068187 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/068187
Repairing monolithic stacked integrated circuits with a redundant layer and lithography process Oct 30, 2013 Issued
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