
Caleb E. Henry
Examiner (ID: 4374, Phone: (571)270-5370 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2818, 2894 |
| Total Applications | 1559 |
| Issued Applications | 1303 |
| Pending Applications | 119 |
| Abandoned Applications | 178 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7728040
[patent_doc_number] => 20120012820
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-19
[patent_title] => 'ORGANIC ELECTROLUMINESCENCE DEVICE AND METHOD FOR PRODUCING ORGANIC ELECTROLUMINESCENCE DEVICE'
[patent_app_type] => utility
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Array
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Array
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[patent_title] => 'METHODS FOR ETCHING DOPED OXIDES IN THE MANUFACTURE OF MICROFEATURE DEVICES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/875036 | Methods for etching doped oxides in the manufacture of microfeature devices | Sep 1, 2010 | Issued |
Array
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[patent_title] => 'METHOD FOR THE PRODUCTION OF THIN SUBSTRATES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/872218 | Method for the production of thin layer of silicon by utilization of mismatch in coefficient of thermal expansion between screen printed metal layer and silicon mother substrate | Aug 30, 2010 | Issued |
Array
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Array
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[patent_title] => 'INTEGRATED CIRCUIT ARRANGEMENT WITH AN AUXILIARY INDENTATION, PARTICULARLY WITH ALIGNING MARKS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/854676 | Integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks | Aug 10, 2010 | Issued |
Array
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[id] => 6015846
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[patent_issue_date] => 2011-09-15
[patent_title] => 'PROCESS FOR ASSEMBLING CAMERA MODULE'
[patent_app_type] => utility
[patent_app_number] => 12/848700
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/848700 | PROCESS FOR ASSEMBLING CAMERA MODULE | Aug 1, 2010 | Abandoned |
Array
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[patent_doc_number] => 20110165747
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[patent_kind] => A1
[patent_issue_date] => 2011-07-07
[patent_title] => 'SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/840027
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Array
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[id] => 9299731
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[patent_title] => 'Method for fabricating semiconductor device having expanded critical dimension by performining surface treatment'
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Array
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[id] => 9099478
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[patent_issue_date] => 2013-10-22
[patent_title] => 'Method for manufacturing photovoltaic device'
[patent_app_type] => utility
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Array
(
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Array
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Array
(
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Array
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Array
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Array
(
[id] => 7488965
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/764763 | Semiconductor device having a junction of P type pillar region and N type pillar region | Apr 20, 2010 | Issued |