Search

Caleb E. Henry

Examiner (ID: 4374, Phone: (571)270-5370 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2818, 2894
Total Applications
1559
Issued Applications
1303
Pending Applications
119
Abandoned Applications
178

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7728040 [patent_doc_number] => 20120012820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'ORGANIC ELECTROLUMINESCENCE DEVICE AND METHOD FOR PRODUCING ORGANIC ELECTROLUMINESCENCE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/894066 [patent_app_country] => US [patent_app_date] => 2010-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 16263 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20120012820.pdf [firstpage_image] =>[orig_patent_app_number] => 12894066 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/894066
Organic electroluminescence device and a method for producing the device Sep 28, 2010 Issued
Array ( [id] => 8875653 [patent_doc_number] => 08470618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Method of manufacturing a light-emitting diode having electrically active and passive portions' [patent_app_type] => utility [patent_app_number] => 12/882868 [patent_app_country] => US [patent_app_date] => 2010-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3968 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12882868 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/882868
Method of manufacturing a light-emitting diode having electrically active and passive portions Sep 14, 2010 Issued
Array ( [id] => 6348409 [patent_doc_number] => 20100330768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'METHODS FOR ETCHING DOPED OXIDES IN THE MANUFACTURE OF MICROFEATURE DEVICES' [patent_app_type] => utility [patent_app_number] => 12/875036 [patent_app_country] => US [patent_app_date] => 2010-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0330/20100330768.pdf [firstpage_image] =>[orig_patent_app_number] => 12875036 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875036
Methods for etching doped oxides in the manufacture of microfeature devices Sep 1, 2010 Issued
Array ( [id] => 6609678 [patent_doc_number] => 20100323472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'METHOD FOR THE PRODUCTION OF THIN SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 12/872218 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0323/20100323472.pdf [firstpage_image] =>[orig_patent_app_number] => 12872218 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/872218
Method for the production of thin layer of silicon by utilization of mismatch in coefficient of thermal expansion between screen printed metal layer and silicon mother substrate Aug 30, 2010 Issued
Array ( [id] => 9310148 [patent_doc_number] => 08651359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Flip chip bonder head for forming a uniform fillet' [patent_app_type] => utility [patent_app_number] => 12/861017 [patent_app_country] => US [patent_app_date] => 2010-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 7012 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12861017 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/861017
Flip chip bonder head for forming a uniform fillet Aug 22, 2010 Issued
Array ( [id] => 6571615 [patent_doc_number] => 20100320613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'INTEGRATED CIRCUIT ARRANGEMENT WITH AN AUXILIARY INDENTATION, PARTICULARLY WITH ALIGNING MARKS' [patent_app_type] => utility [patent_app_number] => 12/854676 [patent_app_country] => US [patent_app_date] => 2010-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3339 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20100320613.pdf [firstpage_image] =>[orig_patent_app_number] => 12854676 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/854676
Integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks Aug 10, 2010 Issued
Array ( [id] => 6015846 [patent_doc_number] => 20110223705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'PROCESS FOR ASSEMBLING CAMERA MODULE' [patent_app_type] => utility [patent_app_number] => 12/848700 [patent_app_country] => US [patent_app_date] => 2010-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3862 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20110223705.pdf [firstpage_image] =>[orig_patent_app_number] => 12848700 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/848700
PROCESS FOR ASSEMBLING CAMERA MODULE Aug 1, 2010 Abandoned
Array ( [id] => 6102254 [patent_doc_number] => 20110165747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/840027 [patent_app_country] => US [patent_app_date] => 2010-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2595 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20110165747.pdf [firstpage_image] =>[orig_patent_app_number] => 12840027 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/840027
SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF Jul 19, 2010 Abandoned
Array ( [id] => 9299731 [patent_doc_number] => 08647958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Method for fabricating semiconductor device having expanded critical dimension by performining surface treatment' [patent_app_type] => utility [patent_app_number] => 12/832187 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3909 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12832187 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/832187
Method for fabricating semiconductor device having expanded critical dimension by performining surface treatment Jul 7, 2010 Issued
Array ( [id] => 9099478 [patent_doc_number] => 08563351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Method for manufacturing photovoltaic device' [patent_app_type] => utility [patent_app_number] => 12/823667 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12823667 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/823667
Method for manufacturing photovoltaic device Jun 24, 2010 Issued
Array ( [id] => 6484673 [patent_doc_number] => 20100258906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/821093 [patent_app_country] => US [patent_app_date] => 2010-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1853 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20100258906.pdf [firstpage_image] =>[orig_patent_app_number] => 12821093 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/821093
CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Jun 21, 2010 Abandoned
Array ( [id] => 7651404 [patent_doc_number] => 20110300673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'POST-DISPENSE VACUUM OVEN FOR REDUCING UNDERFILL VOIDS DURING IC ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 12/796430 [patent_app_country] => US [patent_app_date] => 2010-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3181 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20110300673.pdf [firstpage_image] =>[orig_patent_app_number] => 12796430 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/796430
POST-DISPENSE VACUUM OVEN FOR REDUCING UNDERFILL VOIDS DURING IC ASSEMBLY Jun 7, 2010 Abandoned
Array ( [id] => 6624733 [patent_doc_number] => 20100311245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'SUBSTRATE PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 12/792863 [patent_app_country] => US [patent_app_date] => 2010-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10826 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0311/20100311245.pdf [firstpage_image] =>[orig_patent_app_number] => 12792863 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/792863
SUBSTRATE PROCESSING METHOD Jun 2, 2010 Abandoned
Array ( [id] => 8579214 [patent_doc_number] => 08345434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'High frequency circuit having multi-chip module structure' [patent_app_type] => utility [patent_app_number] => 12/786942 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 8591 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12786942 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786942
High frequency circuit having multi-chip module structure May 24, 2010 Issued
Array ( [id] => 4634881 [patent_doc_number] => 08013334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Bonding structure of circuit substrate for instant circuit inspecting' [patent_app_type] => utility [patent_app_number] => 12/775766 [patent_app_country] => US [patent_app_date] => 2010-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2514 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/013/08013334.pdf [firstpage_image] =>[orig_patent_app_number] => 12775766 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/775766
Bonding structure of circuit substrate for instant circuit inspecting May 6, 2010 Issued
Array ( [id] => 7488965 [patent_doc_number] => 20110237012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'METHOD FOR FABRICATING NOVEL HIGH-PERFORMANCE FIELD-EFFECT TRANSISTOR BIOSENSOR BASED ON CONDUCTIVE POLYMER NANOMATERIALS FUNCTIONALIZED WITH ANTI-VEGF ADAPTER' [patent_app_type] => utility [patent_app_number] => 12/766280 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5525 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20110237012.pdf [firstpage_image] =>[orig_patent_app_number] => 12766280 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/766280
Method for fabricating novel high-performance field-effect transistor biosensor based on conductive polymer nanomaterials functionalized with anti-VEGF adapter Apr 22, 2010 Issued
Array ( [id] => 8571590 [patent_doc_number] => 08338235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Package process of stacked type semiconductor device package structure' [patent_app_type] => utility [patent_app_number] => 12/766549 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 4392 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12766549 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/766549
Package process of stacked type semiconductor device package structure Apr 22, 2010 Issued
Array ( [id] => 7499982 [patent_doc_number] => 20110262712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'METHOD FOR INCREASING THE WORKING SURFACE AREA OF A PHOTOVOLTAIC (PV) MODULE AND ASSOCIATED SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 12/765340 [patent_app_country] => US [patent_app_date] => 2010-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3683 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20110262712.pdf [firstpage_image] =>[orig_patent_app_number] => 12765340 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/765340
METHOD FOR INCREASING THE WORKING SURFACE AREA OF A PHOTOVOLTAIC (PV) MODULE AND ASSOCIATED SUBSTRATES Apr 21, 2010 Abandoned
Array ( [id] => 7500691 [patent_doc_number] => 20110263074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'APPARATUS AND METHODS FOR REDUCING LIGHT INDUCED DAMAGE IN THIN FILM SOLAR CELLS' [patent_app_type] => utility [patent_app_number] => 12/765458 [patent_app_country] => US [patent_app_date] => 2010-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20110263074.pdf [firstpage_image] =>[orig_patent_app_number] => 12765458 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/765458
APPARATUS AND METHODS FOR REDUCING LIGHT INDUCED DAMAGE IN THIN FILM SOLAR CELLS Apr 21, 2010 Abandoned
Array ( [id] => 6494586 [patent_doc_number] => 20100200936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/764763 [patent_app_country] => US [patent_app_date] => 2010-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 16323 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20100200936.pdf [firstpage_image] =>[orig_patent_app_number] => 12764763 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/764763
Semiconductor device having a junction of P type pillar region and N type pillar region Apr 20, 2010 Issued
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