Search

Caleb E. Henry

Examiner (ID: 13871, Phone: (571)270-5370 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2818, 2894
Total Applications
1607
Issued Applications
1337
Pending Applications
112
Abandoned Applications
182

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6624733 [patent_doc_number] => 20100311245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'SUBSTRATE PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 12/792863 [patent_app_country] => US [patent_app_date] => 2010-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10826 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0311/20100311245.pdf [firstpage_image] =>[orig_patent_app_number] => 12792863 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/792863
SUBSTRATE PROCESSING METHOD Jun 2, 2010 Abandoned
Array ( [id] => 8579214 [patent_doc_number] => 08345434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'High frequency circuit having multi-chip module structure' [patent_app_type] => utility [patent_app_number] => 12/786942 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 8591 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12786942 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786942
High frequency circuit having multi-chip module structure May 24, 2010 Issued
Array ( [id] => 4634881 [patent_doc_number] => 08013334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Bonding structure of circuit substrate for instant circuit inspecting' [patent_app_type] => utility [patent_app_number] => 12/775766 [patent_app_country] => US [patent_app_date] => 2010-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2514 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/013/08013334.pdf [firstpage_image] =>[orig_patent_app_number] => 12775766 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/775766
Bonding structure of circuit substrate for instant circuit inspecting May 6, 2010 Issued
Array ( [id] => 7488965 [patent_doc_number] => 20110237012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'METHOD FOR FABRICATING NOVEL HIGH-PERFORMANCE FIELD-EFFECT TRANSISTOR BIOSENSOR BASED ON CONDUCTIVE POLYMER NANOMATERIALS FUNCTIONALIZED WITH ANTI-VEGF ADAPTER' [patent_app_type] => utility [patent_app_number] => 12/766280 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5525 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20110237012.pdf [firstpage_image] =>[orig_patent_app_number] => 12766280 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/766280
Method for fabricating novel high-performance field-effect transistor biosensor based on conductive polymer nanomaterials functionalized with anti-VEGF adapter Apr 22, 2010 Issued
Array ( [id] => 8571590 [patent_doc_number] => 08338235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Package process of stacked type semiconductor device package structure' [patent_app_type] => utility [patent_app_number] => 12/766549 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 4392 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12766549 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/766549
Package process of stacked type semiconductor device package structure Apr 22, 2010 Issued
Array ( [id] => 7499982 [patent_doc_number] => 20110262712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'METHOD FOR INCREASING THE WORKING SURFACE AREA OF A PHOTOVOLTAIC (PV) MODULE AND ASSOCIATED SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 12/765340 [patent_app_country] => US [patent_app_date] => 2010-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3683 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20110262712.pdf [firstpage_image] =>[orig_patent_app_number] => 12765340 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/765340
METHOD FOR INCREASING THE WORKING SURFACE AREA OF A PHOTOVOLTAIC (PV) MODULE AND ASSOCIATED SUBSTRATES Apr 21, 2010 Abandoned
Array ( [id] => 7500691 [patent_doc_number] => 20110263074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'APPARATUS AND METHODS FOR REDUCING LIGHT INDUCED DAMAGE IN THIN FILM SOLAR CELLS' [patent_app_type] => utility [patent_app_number] => 12/765458 [patent_app_country] => US [patent_app_date] => 2010-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20110263074.pdf [firstpage_image] =>[orig_patent_app_number] => 12765458 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/765458
APPARATUS AND METHODS FOR REDUCING LIGHT INDUCED DAMAGE IN THIN FILM SOLAR CELLS Apr 21, 2010 Abandoned
Array ( [id] => 6494586 [patent_doc_number] => 20100200936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/764763 [patent_app_country] => US [patent_app_date] => 2010-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 16323 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20100200936.pdf [firstpage_image] =>[orig_patent_app_number] => 12764763 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/764763
Semiconductor device having a junction of P type pillar region and N type pillar region Apr 20, 2010 Issued
Array ( [id] => 7510972 [patent_doc_number] => 20110256682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 12/761159 [patent_app_country] => US [patent_app_date] => 2010-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6125 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20110256682.pdf [firstpage_image] =>[orig_patent_app_number] => 12761159 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/761159
Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device Apr 14, 2010 Abandoned
Array ( [id] => 6235470 [patent_doc_number] => 20100267174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'LED Substrate Processing' [patent_app_type] => utility [patent_app_number] => 12/761319 [patent_app_country] => US [patent_app_date] => 2010-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6663 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20100267174.pdf [firstpage_image] =>[orig_patent_app_number] => 12761319 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/761319
LED substrate processing Apr 14, 2010 Issued
Array ( [id] => 7511022 [patent_doc_number] => 20110256732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'Pulsed Plasma to Affect Conformal Processing' [patent_app_type] => utility [patent_app_number] => 12/760847 [patent_app_country] => US [patent_app_date] => 2010-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3649 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20110256732.pdf [firstpage_image] =>[orig_patent_app_number] => 12760847 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/760847
Pulsed plasma to affect conformal processing Apr 14, 2010 Issued
Array ( [id] => 6235541 [patent_doc_number] => 20100267245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'HIGH EFFICIENCY EPITAXIAL CHEMICAL VAPOR DEPOSITION (CVD) REACTOR' [patent_app_type] => utility [patent_app_number] => 12/759820 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20100267245.pdf [firstpage_image] =>[orig_patent_app_number] => 12759820 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/759820
High efficiency epitaxial chemical vapor deposition (CVD) reactor Apr 13, 2010 Issued
Array ( [id] => 6512222 [patent_doc_number] => 20100261313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF PACKAGING SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 12/758820 [patent_app_country] => US [patent_app_date] => 2010-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20100261313.pdf [firstpage_image] =>[orig_patent_app_number] => 12758820 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/758820
Semiconductor package and method of packaging semiconductor devices Apr 12, 2010 Issued
Array ( [id] => 6512649 [patent_doc_number] => 20100261347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME8027' [patent_app_type] => utility [patent_app_number] => 12/758868 [patent_app_country] => US [patent_app_date] => 2010-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7491 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20100261347.pdf [firstpage_image] =>[orig_patent_app_number] => 12758868 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/758868
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME8027 Apr 12, 2010 Abandoned
Array ( [id] => 8796936 [patent_doc_number] => 08435803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-07 [patent_title] => 'Method for depositing microcrystalline silicon and monitor device of plasma enhanced deposition' [patent_app_type] => utility [patent_app_number] => 12/758698 [patent_app_country] => US [patent_app_date] => 2010-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2194 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12758698 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/758698
Method for depositing microcrystalline silicon and monitor device of plasma enhanced deposition Apr 11, 2010 Issued
Array ( [id] => 6512236 [patent_doc_number] => 20100261314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'THERMOSETTING DIE BONDING FILM' [patent_app_type] => utility [patent_app_number] => 12/755810 [patent_app_country] => US [patent_app_date] => 2010-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 14387 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20100261314.pdf [firstpage_image] =>[orig_patent_app_number] => 12755810 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/755810
THERMOSETTING DIE BONDING FILM Apr 6, 2010 Abandoned
Array ( [id] => 6235531 [patent_doc_number] => 20100267235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'METHODS FOR DEPOSITING ULTRA THIN LOW RESISTIVITY TUNGSTEN FILM FOR SMALL CRITICAL DIMENSION CONTACTS AND INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 12/755259 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20100267235.pdf [firstpage_image] =>[orig_patent_app_number] => 12755259 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/755259
Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects Apr 5, 2010 Issued
Array ( [id] => 6512625 [patent_doc_number] => 20100261345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/750959 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8237 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20100261345.pdf [firstpage_image] =>[orig_patent_app_number] => 12750959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/750959
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE Mar 30, 2010 Abandoned
Array ( [id] => 8421703 [patent_doc_number] => 08278191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Methods and systems for metal-assisted chemical etching of substrates' [patent_app_type] => utility [patent_app_number] => 12/751080 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 8941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12751080 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751080
Methods and systems for metal-assisted chemical etching of substrates Mar 30, 2010 Issued
Array ( [id] => 6345658 [patent_doc_number] => 20100248484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'Methods of Forming Printable Integrated Circuit Devices and Devices Formed Thereby' [patent_app_type] => utility [patent_app_number] => 12/732868 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5662 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20100248484.pdf [firstpage_image] =>[orig_patent_app_number] => 12732868 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/732868
Methods of forming printable integrated circuit devices by selective etching to suspend the devices from a handling substrate and devices formed thereby Mar 25, 2010 Issued
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