Caleb E. Henry

Array ( [id] => 5391772 [patent_doc_number] => 20090209085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'METHOD FOR REUSING DELAMINATED WAFER' [patent_app_type] => utility [patent_app_number] => 12/308990 [patent_app_country] => US [patent_app_date] => 2007-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5343 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20090209085.pdf [firstpage_image] =>[orig_patent_app_number] => 12308990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7724650 [patent_doc_number] => 08097922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-17 [patent_title] => 'Nanometer-scale transistor architecture providing enhanced carrier mobility' [patent_app_type] => utility [patent_app_number] => 11/754618 [patent_app_country] => US [patent_app_date] => 2007-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4394 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/097/08097922.pdf [firstpage_image] =>[orig_patent_app_number] => 11754618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7967701 [patent_doc_number] => 07939883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Voltage regulating apparatus having a reduced current consumption and settling time' [patent_app_type] => utility [patent_app_number] => 11/754129 [patent_app_country] => US [patent_app_date] => 2007-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4024 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/939/07939883.pdf [firstpage_image] =>[orig_patent_app_number] => 11754129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4789508 [patent_doc_number] => 20080290481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'Semiconductor Device Package Leadframe' [patent_app_type] => utility [patent_app_number] => 11/754108 [patent_app_country] => US [patent_app_date] => 2007-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2402 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20080290481.pdf [firstpage_image] =>[orig_patent_app_number] => 11754108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6265413 [patent_doc_number] => 20100297781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'METHOD FOR MANUFACTURING MEMS STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/308530 [patent_app_country] => US [patent_app_date] => 2007-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2451 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20100297781.pdf [firstpage_image] =>[orig_patent_app_number] => 12308530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4789439 [patent_doc_number] => 20080290412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'SUPPRESSING SHORT CHANNEL EFFECTS' [patent_app_type] => utility [patent_app_number] => 11/751959 [patent_app_country] => US [patent_app_date] => 2007-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4688 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20080290412.pdf [firstpage_image] =>[orig_patent_app_number] => 11751959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5082928 [patent_doc_number] => 20070272979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/748869 [patent_app_country] => US [patent_app_date] => 2007-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 16298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20070272979.pdf [firstpage_image] =>[orig_patent_app_number] => 11748869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5088825 [patent_doc_number] => 20070228464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'MOS transistor' [patent_app_type] => utility [patent_app_number] => 11/748479 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4073 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20070228464.pdf [firstpage_image] =>[orig_patent_app_number] => 11748479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4837710 [patent_doc_number] => 20080278213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'HIGH OHMIC INTEGRATED RESISTOR WITH IMPROVED LINEARITY' [patent_app_type] => utility [patent_app_number] => 11/746949 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3590 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20080278213.pdf [firstpage_image] =>[orig_patent_app_number] => 11746949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4876636 [patent_doc_number] => 20080150019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'PROFILED GATE FIELD EFFECT TRANSISTOR WITH ENHANCED HIGH HARMONIC GAIN' [patent_app_type] => utility [patent_app_number] => 11/746088 [patent_app_country] => US [patent_app_date] => 2007-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150019.pdf [firstpage_image] =>[orig_patent_app_number] => 11746088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5582712 [patent_doc_number] => 20090101914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'Semiconductor Image Sensing Device' [patent_app_type] => utility [patent_app_number] => 12/227159 [patent_app_country] => US [patent_app_date] => 2007-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11649 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20090101914.pdf [firstpage_image] =>[orig_patent_app_number] => 12227159 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7763515 [patent_doc_number] => 08115251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Recessed gate channel with low Vt corner' [patent_app_type] => utility [patent_app_number] => 11/741898 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 8674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/115/08115251.pdf [firstpage_image] =>[orig_patent_app_number] => 11741898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4856494 [patent_doc_number] => 20080265344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/DRAIN OF A SEMICONDUCTOR DEVICE, AND RELATED DEVICE' [patent_app_type] => utility [patent_app_number] => 11/741519 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6887 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265344.pdf [firstpage_image] =>[orig_patent_app_number] => 11741519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5165657 [patent_doc_number] => 20070287244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'ALTERNATIVE INTEGRATION SCHEME FOR CMOS S/D SiGe PROCESS' [patent_app_type] => utility [patent_app_number] => 11/739099 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9489 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20070287244.pdf [firstpage_image] =>[orig_patent_app_number] => 11739099 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 102458 [patent_doc_number] => 07723207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Three dimensional integrated circuit and method of design' [patent_app_type] => utility [patent_app_number] => 11/737598 [patent_app_country] => US [patent_app_date] => 2007-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3557 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/723/07723207.pdf [firstpage_image] =>[orig_patent_app_number] => 11737598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4539299 [patent_doc_number] => 07875531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Method for the production of thin substrates' [patent_app_type] => utility [patent_app_number] => 11/736929 [patent_app_country] => US [patent_app_date] => 2007-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 12983 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/875/07875531.pdf [firstpage_image] =>[orig_patent_app_number] => 11736929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9112973 [patent_doc_number] => 08569142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/736408 [patent_app_country] => US [patent_app_date] => 2007-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11736408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10876185 [patent_doc_number] => 08900970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Method for manufacturing a semiconductor device using a flexible substrate' [patent_app_type] => utility [patent_app_number] => 11/735009 [patent_app_country] => US [patent_app_date] => 2007-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 46 [patent_no_of_words] => 15183 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11735009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 111688 [patent_doc_number] => 07718513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Forming silicided gate and contacts from polysilicon germanium and structure formed' [patent_app_type] => utility [patent_app_number] => 11/734888 [patent_app_country] => US [patent_app_date] => 2007-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1904 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/718/07718513.pdf [firstpage_image] =>[orig_patent_app_number] => 11734888 [rel_patent_id] =>[rel_patent_doc_number] =>)