
Caleb E. Henry
Examiner (ID: 13871, Phone: (571)270-5370 , Office: P/2894 )
| Most Active Art Unit | 2894 |
| Art Unit(s) | 2818, 2894 |
| Total Applications | 1607 |
| Issued Applications | 1337 |
| Pending Applications | 112 |
| Abandoned Applications | 182 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7763515
[patent_doc_number] => 08115251
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-14
[patent_title] => 'Recessed gate channel with low Vt corner'
[patent_app_type] => utility
[patent_app_number] => 11/741898
[patent_app_country] => US
[patent_app_date] => 2007-04-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/08/115/08115251.pdf
[firstpage_image] =>[orig_patent_app_number] => 11741898
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741898 | Recessed gate channel with low Vt corner | Apr 29, 2007 | Issued |
Array
(
[id] => 4856494
[patent_doc_number] => 20080265344
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/DRAIN OF A SEMICONDUCTOR DEVICE, AND RELATED DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/741519
[patent_app_country] => US
[patent_app_date] => 2007-04-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0265/20080265344.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741519 | Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device | Apr 26, 2007 | Issued |
Array
(
[id] => 5165657
[patent_doc_number] => 20070287244
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-13
[patent_title] => 'ALTERNATIVE INTEGRATION SCHEME FOR CMOS S/D SiGe PROCESS'
[patent_app_type] => utility
[patent_app_number] => 11/739099
[patent_app_country] => US
[patent_app_date] => 2007-04-24
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/739099 | ALTERNATIVE INTEGRATION SCHEME FOR CMOS S/D SiGe PROCESS | Apr 23, 2007 | Abandoned |
Array
(
[id] => 102458
[patent_doc_number] => 07723207
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-25
[patent_title] => 'Three dimensional integrated circuit and method of design'
[patent_app_type] => utility
[patent_app_number] => 11/737598
[patent_app_country] => US
[patent_app_date] => 2007-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/737598 | Three dimensional integrated circuit and method of design | Apr 18, 2007 | Issued |
Array
(
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[patent_issue_date] => 2011-01-25
[patent_title] => 'Method for the production of thin substrates'
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[patent_app_country] => US
[patent_app_date] => 2007-04-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/736929 | Method for the production of thin substrates | Apr 17, 2007 | Issued |
Array
(
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[patent_issue_date] => 2013-10-29
[patent_title] => 'Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/736408 | Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same | Apr 16, 2007 | Issued |
Array
(
[id] => 10876185
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[patent_issue_date] => 2014-12-02
[patent_title] => 'Method for manufacturing a semiconductor device using a flexible substrate'
[patent_app_type] => utility
[patent_app_number] => 11/735009
[patent_app_country] => US
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Array
(
[id] => 8018127
[patent_doc_number] => 08138568
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-20
[patent_title] => 'Transparent carbon nanotube electrode using conductive dispersant and production method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/735178
[patent_app_country] => US
[patent_app_date] => 2007-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/08/138/08138568.pdf
[firstpage_image] =>[orig_patent_app_number] => 11735178
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/735178 | Transparent carbon nanotube electrode using conductive dispersant and production method thereof | Apr 12, 2007 | Issued |
Array
(
[id] => 111688
[patent_doc_number] => 07718513
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-18
[patent_title] => 'Forming silicided gate and contacts from polysilicon germanium and structure formed'
[patent_app_type] => utility
[patent_app_number] => 11/734888
[patent_app_country] => US
[patent_app_date] => 2007-04-13
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[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/07/718/07718513.pdf
[firstpage_image] =>[orig_patent_app_number] => 11734888
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/734888 | Forming silicided gate and contacts from polysilicon germanium and structure formed | Apr 12, 2007 | Issued |
Array
(
[id] => 4660893
[patent_doc_number] => 20080251800
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-16
[patent_title] => 'Undoped and Unintentionally Doped Buffer Structures'
[patent_app_type] => utility
[patent_app_number] => 11/734218
[patent_app_country] => US
[patent_app_date] => 2007-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0251/20080251800.pdf
[firstpage_image] =>[orig_patent_app_number] => 11734218
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/734218 | Light emitting diode having undoped and unintentionally doped nitride transition layer | Apr 10, 2007 | Issued |
Array
(
[id] => 4506766
[patent_doc_number] => 07915089
[patent_country] => US
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[patent_issue_date] => 2011-03-29
[patent_title] => 'Encapsulation method'
[patent_app_type] => utility
[patent_app_number] => 11/733289
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11733289
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/733289 | Encapsulation method | Apr 9, 2007 | Issued |
Array
(
[id] => 5069631
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[patent_title] => 'Transistors of Semiconductor Devices and Methods of Fabricating the Same'
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Array
(
[id] => 5210489
[patent_doc_number] => 20070249073
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[patent_title] => 'Method for determining the electrically active dopant density profile in ultra-shallow junction (USJ) structures'
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Array
(
[id] => 4817064
[patent_doc_number] => 20080224323
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[patent_issue_date] => 2008-09-18
[patent_title] => 'Semiconductor Module With Semiconductor Chips And Method For Producing It'
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[patent_app_number] => 11/693333
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/693333 | Semiconductor module with multiple semiconductor chips | Mar 28, 2007 | Issued |
Array
(
[id] => 4715345
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[patent_title] => 'LOW CONTACT RESISTANCE METAL CONTACT'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11692227
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/692227 | Low contact resistance metal contact | Mar 27, 2007 | Issued |
Array
(
[id] => 91952
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[patent_issue_date] => 2010-06-08
[patent_title] => 'Semiconductor device having self-aligned epitaxial source and drain extensions'
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[patent_app_number] => 11/729189
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/729189 | Semiconductor device having self-aligned epitaxial source and drain extensions | Mar 27, 2007 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/224879 | Method of manufacturing semiconductor device including removal of deposits from process chamber and supply portion | Mar 26, 2007 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/450315 | ORGANIC SEMICONDUCTOR ELEMENT AND MANUFACTURE METHOD THEREOF | Mar 25, 2007 | Abandoned |
Array
(
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[patent_app_number] => 11/690494
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/690494 | Method for producing a semiconductor component | Mar 22, 2007 | Issued |