Search

Caleb E. Henry

Examiner (ID: 4374, Phone: (571)270-5370 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2818, 2894
Total Applications
1559
Issued Applications
1303
Pending Applications
119
Abandoned Applications
178

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4982954 [patent_doc_number] => 20070087512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Substrate embedded with passive device' [patent_app_type] => utility [patent_app_number] => 11/546358 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3096 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087512.pdf [firstpage_image] =>[orig_patent_app_number] => 11546358 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546358
Substrate embedded with passive device Oct 11, 2006 Issued
Array ( [id] => 5300131 [patent_doc_number] => 20090294783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Process to fabricate integrated mwir emitter' [patent_app_type] => utility [patent_app_number] => 11/919299 [patent_app_country] => US [patent_app_date] => 2006-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2926 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20090294783.pdf [firstpage_image] =>[orig_patent_app_number] => 11919299 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/919299
Process to fabricate integrated MWIR emitter Oct 1, 2006 Issued
Array ( [id] => 5275565 [patent_doc_number] => 20090127697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'Housing with a Cavity for a Mechanically-Sensitive Electronic Component and Method for Production' [patent_app_type] => utility [patent_app_number] => 12/090529 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8254 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20090127697.pdf [firstpage_image] =>[orig_patent_app_number] => 12090529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/090529
Housing with a Cavity for a Mechanically-Sensitive Electronic Component and Method for Production Sep 28, 2006 Abandoned
Array ( [id] => 5377309 [patent_doc_number] => 20090189148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'TRANSISTOR ELEMENT, DISPLAY DEVICE AND THESE MANUFACTURING METHODS' [patent_app_type] => utility [patent_app_number] => 12/067251 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8795 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20090189148.pdf [firstpage_image] =>[orig_patent_app_number] => 12067251 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/067251
TRANSISTOR ELEMENT, DISPLAY DEVICE AND THESE MANUFACTURING METHODS Sep 27, 2006 Abandoned
Array ( [id] => 4938910 [patent_doc_number] => 20080076229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Method to form decoupling capacitors on IC chip and the structure thereof' [patent_app_type] => utility [patent_app_number] => 11/527488 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1248 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20080076229.pdf [firstpage_image] =>[orig_patent_app_number] => 11527488 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/527488
Method to form decoupling capacitors on IC chip and the structure thereof Sep 26, 2006 Abandoned
Array ( [id] => 5171894 [patent_doc_number] => 20070072327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method of Forming an Integrated MEMS Resonator' [patent_app_type] => utility [patent_app_number] => 11/535698 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072327.pdf [firstpage_image] =>[orig_patent_app_number] => 11535698 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/535698
Method of forming an integrated MEMS resonator Sep 26, 2006 Issued
Array ( [id] => 5171970 [patent_doc_number] => 20070072403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/526698 [patent_app_country] => US [patent_app_date] => 2006-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2974 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072403.pdf [firstpage_image] =>[orig_patent_app_number] => 11526698 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/526698
Semiconductor device and method for fabricating the same Sep 25, 2006 Abandoned
Array ( [id] => 5031723 [patent_doc_number] => 20070096262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Method for manufacturing nitride semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 11/525906 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5061 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096262.pdf [firstpage_image] =>[orig_patent_app_number] => 11525906 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/525906
Method for manufacturing nitride semiconductor substrate Sep 24, 2006 Issued
Array ( [id] => 23606 [patent_doc_number] => 07795105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement' [patent_app_type] => utility [patent_app_number] => 11/527736 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3313 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/795/07795105.pdf [firstpage_image] =>[orig_patent_app_number] => 11527736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/527736
Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement Sep 24, 2006 Issued
Array ( [id] => 359601 [patent_doc_number] => 07485480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method of manufacturing high power light-emitting device package and structure thereof' [patent_app_type] => utility [patent_app_number] => 11/524462 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4929 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/485/07485480.pdf [firstpage_image] =>[orig_patent_app_number] => 11524462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/524462
Method of manufacturing high power light-emitting device package and structure thereof Sep 20, 2006 Issued
Array ( [id] => 232758 [patent_doc_number] => 07598183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Bi-layer capping of low-K dielectric films' [patent_app_type] => utility [patent_app_number] => 11/533505 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6080 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/598/07598183.pdf [firstpage_image] =>[orig_patent_app_number] => 11533505 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/533505
Bi-layer capping of low-K dielectric films Sep 19, 2006 Issued
Array ( [id] => 299828 [patent_doc_number] => 07538027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Fabrication method for semiconductor interconnections' [patent_app_type] => utility [patent_app_number] => 11/532796 [patent_app_country] => US [patent_app_date] => 2006-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 8395 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538027.pdf [firstpage_image] =>[orig_patent_app_number] => 11532796 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/532796
Fabrication method for semiconductor interconnections Sep 17, 2006 Issued
Array ( [id] => 315176 [patent_doc_number] => 07525146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Nonvolatile semiconductor memory devices' [patent_app_type] => utility [patent_app_number] => 11/520886 [patent_app_country] => US [patent_app_date] => 2006-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 7195 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/525/07525146.pdf [firstpage_image] =>[orig_patent_app_number] => 11520886 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/520886
Nonvolatile semiconductor memory devices Sep 13, 2006 Issued
Array ( [id] => 4922025 [patent_doc_number] => 20080070340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Image sensor using thin-film SOI' [patent_app_type] => utility [patent_app_number] => 11/520958 [patent_app_country] => US [patent_app_date] => 2006-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15936 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20080070340.pdf [firstpage_image] =>[orig_patent_app_number] => 11520958 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/520958
Image sensor using thin-film SOI Sep 13, 2006 Abandoned
Array ( [id] => 5056949 [patent_doc_number] => 20070059871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/519818 [patent_app_country] => US [patent_app_date] => 2006-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3271 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20070059871.pdf [firstpage_image] =>[orig_patent_app_number] => 11519818 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/519818
Semiconductor device and manufacturing method thereof Sep 12, 2006 Issued
Array ( [id] => 4701926 [patent_doc_number] => 20080061448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'SYSTEM AND METHOD FOR THERMAL EXPANSION PRE-COMPENSATED PACKAGE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 11/530925 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2724 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20080061448.pdf [firstpage_image] =>[orig_patent_app_number] => 11530925 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/530925
SYSTEM AND METHOD FOR THERMAL EXPANSION PRE-COMPENSATED PACKAGE SUBSTRATE Sep 11, 2006 Abandoned
Array ( [id] => 4704674 [patent_doc_number] => 20080064198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Chalcogenide semiconductor memory device with insulating dielectric' [patent_app_type] => utility [patent_app_number] => 11/518818 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2722 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20080064198.pdf [firstpage_image] =>[orig_patent_app_number] => 11518818 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518818
Chalcogenide semiconductor memory device with insulating dielectric Sep 10, 2006 Abandoned
Array ( [id] => 93134 [patent_doc_number] => 07732902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Semiconductor package with getter formed over an irregular structure' [patent_app_type] => utility [patent_app_number] => 11/516469 [patent_app_country] => US [patent_app_date] => 2006-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3731 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/732/07732902.pdf [firstpage_image] =>[orig_patent_app_number] => 11516469 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/516469
Semiconductor package with getter formed over an irregular structure Sep 4, 2006 Issued
Array ( [id] => 5171916 [patent_doc_number] => 20070072349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Manufacturing method of a display device' [patent_app_type] => utility [patent_app_number] => 11/509739 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5718 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072349.pdf [firstpage_image] =>[orig_patent_app_number] => 11509739 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/509739
Manufacturing method of a display device Aug 24, 2006 Issued
Array ( [id] => 4982989 [patent_doc_number] => 20070087547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Wafer structure with electroless plating metal connecting layer and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/509876 [patent_app_country] => US [patent_app_date] => 2006-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2345 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087547.pdf [firstpage_image] =>[orig_patent_app_number] => 11509876 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/509876
Wafer structure with electroless plating metal connecting layer and method for fabricating the same Aug 23, 2006 Abandoned
Menu