Search

Caleb E. Henry

Examiner (ID: 13871, Phone: (571)270-5370 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2818, 2894
Total Applications
1607
Issued Applications
1337
Pending Applications
112
Abandoned Applications
182

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6633318 [patent_doc_number] => 20100173441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'METHOD FOR PROCESSING ELONGATE SUBSTRATES AND SUBSTRATE SECURING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/527029 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9076 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20100173441.pdf [firstpage_image] =>[orig_patent_app_number] => 12527029 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/527029
METHOD FOR PROCESSING ELONGATE SUBSTRATES AND SUBSTRATE SECURING APPARATUS Feb 14, 2007 Abandoned
Array ( [id] => 4691206 [patent_doc_number] => 20080083976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Edge connect wafer level stacking' [patent_app_type] => utility [patent_app_number] => 11/704713 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8033 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20080083976.pdf [firstpage_image] =>[orig_patent_app_number] => 11704713 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/704713
Edge connect wafer level stacking with leads extending along edges Feb 8, 2007 Issued
Array ( [id] => 5110417 [patent_doc_number] => 20070194332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Light active sheet material' [patent_app_type] => utility [patent_app_number] => 11/704044 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 17287 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20070194332.pdf [firstpage_image] =>[orig_patent_app_number] => 11704044 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/704044
Light active sheet material Feb 6, 2007 Abandoned
Array ( [id] => 5294175 [patent_doc_number] => 20090009101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Oled Having Stacked Organic Light-Emitting Units' [patent_app_type] => utility [patent_app_number] => 12/087929 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11216 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20090009101.pdf [firstpage_image] =>[orig_patent_app_number] => 12087929 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/087929
OLED having stacked organic light-emitting units Jan 16, 2007 Issued
Array ( [id] => 5527056 [patent_doc_number] => 20090197133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'METHOD FOR PRODUCING FUEL CELL ELECTRODES AND POLYMER ELECTROLYTE FUEL CELLS HAVING FUEL CELL ELECTRODES' [patent_app_type] => utility [patent_app_number] => 12/090258 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4382 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20090197133.pdf [firstpage_image] =>[orig_patent_app_number] => 12090258 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/090258
METHOD FOR PRODUCING FUEL CELL ELECTRODES AND POLYMER ELECTROLYTE FUEL CELLS HAVING FUEL CELL ELECTRODES Dec 6, 2006 Abandoned
Array ( [id] => 8528197 [patent_doc_number] => 08304769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Active matrix substrate having channel protection film covering transistor channel, and display apparatus and/or, television receiver including same' [patent_app_type] => utility [patent_app_number] => 12/224679 [patent_app_country] => US [patent_app_date] => 2006-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 19232 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12224679 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/224679
Active matrix substrate having channel protection film covering transistor channel, and display apparatus and/or, television receiver including same Dec 4, 2006 Issued
Array ( [id] => 5397880 [patent_doc_number] => 20090317943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'Alignment of Semiconducting Nanowires on Metal Electrodes' [patent_app_type] => utility [patent_app_number] => 12/374750 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2500 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0317/20090317943.pdf [firstpage_image] =>[orig_patent_app_number] => 12374750 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/374750
Alignment of Semiconducting Nanowires on Metal Electrodes Nov 27, 2006 Abandoned
Array ( [id] => 5146260 [patent_doc_number] => 20070046314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Process for testing IC wafer' [patent_app_type] => utility [patent_app_number] => 11/589735 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1748 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20070046314.pdf [firstpage_image] =>[orig_patent_app_number] => 11589735 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/589735
Process for testing IC wafer Oct 30, 2006 Abandoned
Array ( [id] => 4982954 [patent_doc_number] => 20070087512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Substrate embedded with passive device' [patent_app_type] => utility [patent_app_number] => 11/546358 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3096 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087512.pdf [firstpage_image] =>[orig_patent_app_number] => 11546358 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546358
Substrate embedded with passive device Oct 11, 2006 Issued
Array ( [id] => 5300131 [patent_doc_number] => 20090294783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Process to fabricate integrated mwir emitter' [patent_app_type] => utility [patent_app_number] => 11/919299 [patent_app_country] => US [patent_app_date] => 2006-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2926 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20090294783.pdf [firstpage_image] =>[orig_patent_app_number] => 11919299 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/919299
Process to fabricate integrated MWIR emitter Oct 1, 2006 Issued
Array ( [id] => 5275565 [patent_doc_number] => 20090127697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'Housing with a Cavity for a Mechanically-Sensitive Electronic Component and Method for Production' [patent_app_type] => utility [patent_app_number] => 12/090529 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8254 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20090127697.pdf [firstpage_image] =>[orig_patent_app_number] => 12090529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/090529
Housing with a Cavity for a Mechanically-Sensitive Electronic Component and Method for Production Sep 28, 2006 Abandoned
Array ( [id] => 5377309 [patent_doc_number] => 20090189148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'TRANSISTOR ELEMENT, DISPLAY DEVICE AND THESE MANUFACTURING METHODS' [patent_app_type] => utility [patent_app_number] => 12/067251 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8795 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20090189148.pdf [firstpage_image] =>[orig_patent_app_number] => 12067251 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/067251
TRANSISTOR ELEMENT, DISPLAY DEVICE AND THESE MANUFACTURING METHODS Sep 27, 2006 Abandoned
Array ( [id] => 4938910 [patent_doc_number] => 20080076229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Method to form decoupling capacitors on IC chip and the structure thereof' [patent_app_type] => utility [patent_app_number] => 11/527488 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1248 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20080076229.pdf [firstpage_image] =>[orig_patent_app_number] => 11527488 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/527488
Method to form decoupling capacitors on IC chip and the structure thereof Sep 26, 2006 Abandoned
Array ( [id] => 5171894 [patent_doc_number] => 20070072327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method of Forming an Integrated MEMS Resonator' [patent_app_type] => utility [patent_app_number] => 11/535698 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072327.pdf [firstpage_image] =>[orig_patent_app_number] => 11535698 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/535698
Method of forming an integrated MEMS resonator Sep 26, 2006 Issued
Array ( [id] => 5171970 [patent_doc_number] => 20070072403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/526698 [patent_app_country] => US [patent_app_date] => 2006-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2974 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072403.pdf [firstpage_image] =>[orig_patent_app_number] => 11526698 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/526698
Semiconductor device and method for fabricating the same Sep 25, 2006 Abandoned
Array ( [id] => 5031723 [patent_doc_number] => 20070096262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Method for manufacturing nitride semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 11/525906 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5061 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096262.pdf [firstpage_image] =>[orig_patent_app_number] => 11525906 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/525906
Method for manufacturing nitride semiconductor substrate Sep 24, 2006 Issued
Array ( [id] => 23606 [patent_doc_number] => 07795105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement' [patent_app_type] => utility [patent_app_number] => 11/527736 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3313 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/795/07795105.pdf [firstpage_image] =>[orig_patent_app_number] => 11527736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/527736
Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement Sep 24, 2006 Issued
Array ( [id] => 359601 [patent_doc_number] => 07485480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method of manufacturing high power light-emitting device package and structure thereof' [patent_app_type] => utility [patent_app_number] => 11/524462 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4929 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/485/07485480.pdf [firstpage_image] =>[orig_patent_app_number] => 11524462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/524462
Method of manufacturing high power light-emitting device package and structure thereof Sep 20, 2006 Issued
Array ( [id] => 232758 [patent_doc_number] => 07598183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Bi-layer capping of low-K dielectric films' [patent_app_type] => utility [patent_app_number] => 11/533505 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6080 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/598/07598183.pdf [firstpage_image] =>[orig_patent_app_number] => 11533505 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/533505
Bi-layer capping of low-K dielectric films Sep 19, 2006 Issued
Array ( [id] => 299828 [patent_doc_number] => 07538027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Fabrication method for semiconductor interconnections' [patent_app_type] => utility [patent_app_number] => 11/532796 [patent_app_country] => US [patent_app_date] => 2006-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 8395 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538027.pdf [firstpage_image] =>[orig_patent_app_number] => 11532796 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/532796
Fabrication method for semiconductor interconnections Sep 17, 2006 Issued
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