Search

Caleen O. Sullivan

Examiner (ID: 789, Phone: (571)272-6569 , Office: P/2896 )

Most Active Art Unit
2899
Art Unit(s)
2896, 1795, 1722, 2899, 1756
Total Applications
1358
Issued Applications
1151
Pending Applications
77
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17158980 [patent_doc_number] => 20210320031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => VERTICAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/356226 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/356226
Vertical semiconductor device and method for fabricating the same Jun 22, 2021 Issued
Array ( [id] => 17158980 [patent_doc_number] => 20210320031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => VERTICAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/356226 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/356226
Vertical semiconductor device and method for fabricating the same Jun 22, 2021 Issued
Array ( [id] => 17158980 [patent_doc_number] => 20210320031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => VERTICAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/356226 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/356226
Vertical semiconductor device and method for fabricating the same Jun 22, 2021 Issued
Array ( [id] => 17158980 [patent_doc_number] => 20210320031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => VERTICAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/356226 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/356226
Vertical semiconductor device and method for fabricating the same Jun 22, 2021 Issued
Array ( [id] => 17145370 [patent_doc_number] => 20210313383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => METAL REFLECTOR GROUNDING FOR NOISE REDUCTION IN LIGHT DETECTOR [patent_app_type] => utility [patent_app_number] => 17/350409 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350409 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350409
Metal reflector grounding for noise reduction in light detector Jun 16, 2021 Issued
Array ( [id] => 18819136 [patent_doc_number] => 20230393476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => PHOTOSENSITIVE ELEMENT AND METHOD FOR PRODUCING PHOTOSENSITIVE ELEMENT [patent_app_type] => utility [patent_app_number] => 18/020874 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18020874 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/020874
PHOTOSENSITIVE ELEMENT AND METHOD FOR PRODUCING PHOTOSENSITIVE ELEMENT Jun 14, 2021 Pending
Array ( [id] => 18564713 [patent_doc_number] => 11729983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Peripheral circuitry under array memory device and method of fabricating thereof [patent_app_type] => utility [patent_app_number] => 17/304049 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 8514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17304049 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/304049
Peripheral circuitry under array memory device and method of fabricating thereof Jun 13, 2021 Issued
Array ( [id] => 17203773 [patent_doc_number] => 20210343868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => RADIATION HARDENED THIN-FILM TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/347155 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17347155 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/347155
Radiation hardened thin-film transistors Jun 13, 2021 Issued
Array ( [id] => 18061681 [patent_doc_number] => 20220392768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => PATTERNING METHOD AND OVERLAY MESUREMENT METHOD [patent_app_type] => utility [patent_app_number] => 17/341183 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341183 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/341183
Patterning method and overlay measurement method Jun 6, 2021 Issued
Array ( [id] => 18613917 [patent_doc_number] => 20230280654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => UPPER FILM-FORMING COMPOSITION AND METHOD FOR PRODUCING PHASE-SEPARATED PATTERN [patent_app_type] => utility [patent_app_number] => 18/007910 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18007910 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/007910
UPPER FILM-FORMING COMPOSITION AND METHOD FOR PRODUCING PHASE-SEPARATED PATTERN Jun 3, 2021 Pending
Array ( [id] => 18040090 [patent_doc_number] => 20220384307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => THERMAL INTERFACE STRUCTURES, ELECTRICAL SYSTEMS WITH THERMAL INTERFACE STRUCTURES, AND METHODS OF MANUFACTURE THEREOF [patent_app_type] => utility [patent_app_number] => 17/335077 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335077 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335077
Thermal interface structures, electrical systems with thermal interface structures, and methods of manufacture thereof May 31, 2021 Issued
Array ( [id] => 18357866 [patent_doc_number] => 11646272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Packaging method of panel-level chip device [patent_app_type] => utility [patent_app_number] => 17/330236 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 40 [patent_no_of_words] => 11906 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/330236
Packaging method of panel-level chip device May 24, 2021 Issued
Array ( [id] => 18514553 [patent_doc_number] => 20230230811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => SURFACE MODIFICATION FOR METAL-CONTAINING PHOTORESIST DEPOSITION [patent_app_type] => utility [patent_app_number] => 17/998354 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -34 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17998354 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/998354
SURFACE MODIFICATION FOR METAL-CONTAINING PHOTORESIST DEPOSITION May 24, 2021 Pending
Array ( [id] => 18453712 [patent_doc_number] => 20230194992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => SYSTEM AND METHOD TO CONTROL DEFECTS IN PROJECTION-BASED SUB-MICROMETER ADDITIVE MANUFACTURING [patent_app_type] => utility [patent_app_number] => 17/926108 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17926108 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/926108
SYSTEM AND METHOD TO CONTROL DEFECTS IN PROJECTION-BASED SUB-MICROMETER ADDITIVE MANUFACTURING May 19, 2021 Pending
Array ( [id] => 17246968 [patent_doc_number] => 20210366713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => METHOD FOR PATTERN REDUCTION USING A STAIRCASE SPACER [patent_app_type] => utility [patent_app_number] => 17/325425 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 463 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325425 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/325425
Method for pattern reduction using a staircase spacer May 19, 2021 Issued
Array ( [id] => 18331851 [patent_doc_number] => 11637108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Memory array circuit and method of manufacturing same [patent_app_type] => utility [patent_app_number] => 17/325641 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 17399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325641 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/325641
Memory array circuit and method of manufacturing same May 19, 2021 Issued
Array ( [id] => 18821129 [patent_doc_number] => 20230395470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => POWER MODULE [patent_app_type] => utility [patent_app_number] => 18/265700 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18265700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/265700
Power module May 16, 2021 Issued
Array ( [id] => 18204387 [patent_doc_number] => 11586782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Guide layout creating apparatus, guide layout creating method and recording medium [patent_app_type] => utility [patent_app_number] => 17/322347 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3605 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322347 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322347
Guide layout creating apparatus, guide layout creating method and recording medium May 16, 2021 Issued
Array ( [id] => 17485889 [patent_doc_number] => 20220093393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES FROM MULTI-DEVICE SEMICONDUCTOR WAFERS [patent_app_type] => utility [patent_app_number] => 17/322412 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322412
Methods of manufacturing semiconductor devices from multi-device semiconductor wafers May 16, 2021 Issued
Array ( [id] => 18447053 [patent_doc_number] => 11682629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Package structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/315372 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 7308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315372 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315372
Package structure and manufacturing method thereof May 9, 2021 Issued
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