Caleen O. Sullivan

Array ( [id] => 16601831 [patent_doc_number] => 20210028362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => DISPLAY DEVICES AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/871128 [patent_app_country] => US [patent_app_date] => 2020-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16871128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16270566 [patent_doc_number] => 20200272053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => COMPOSITION FOR RESIST UNDERLAYER FILM FORMATION, RESIST UNDERLAYER FILM AND FORMING METHOD THEREOF, PATTERNED SUBSTRATE-PRODUCING METHOD, AND COMPOUND [patent_app_type] => utility [patent_app_number] => 16/871131 [patent_app_country] => US [patent_app_date] => 2020-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16871131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16609406 [patent_doc_number] => 10910422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Image sensor package and image sensing module [patent_app_type] => utility [patent_app_number] => 16/868613 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16256837 [patent_doc_number] => 20200266212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => VERTICAL MEMORY DEVICE AND METHOD OF FABRICATION THE SAME [patent_app_type] => utility [patent_app_number] => 16/869581 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16668572 [patent_doc_number] => 10937830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Method of fabricating integrated circuit [patent_app_type] => utility [patent_app_number] => 16/868495 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3114 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16653447 [patent_doc_number] => 10930640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Intelligent diode structures [patent_app_type] => utility [patent_app_number] => 16/861809 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18261794 [patent_doc_number] => 11609494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Semiconductor photoresist composition and method of forming patterns using the composition [patent_app_type] => utility [patent_app_number] => 16/859682 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 9015 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16759923 [patent_doc_number] => 10978480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Three-dimensional semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/856663 [patent_app_country] => US [patent_app_date] => 2020-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 11051 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16560428 [patent_doc_number] => 20210005577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => METHOD FOR INTERCONNECTING STACKED SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/852747 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17999188 [patent_doc_number] => 11500292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Material for forming organic film, substrate for manufacturing semiconductor device, method for forming organic film, patterning process, and compound for forming organic film [patent_app_type] => utility [patent_app_number] => 16/850094 [patent_app_country] => US [patent_app_date] => 2020-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 20811 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16850094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17172106 [patent_doc_number] => 20210325776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => FLUOROPOLYMER STAMP FABRICATION METHOD [patent_app_type] => utility [patent_app_number] => 16/849393 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17862818 [patent_doc_number] => 11443979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/836930 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 42 [patent_no_of_words] => 13364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17145422 [patent_doc_number] => 20210313435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => Sacrificial Layer for Semiconductor Process [patent_app_type] => utility [patent_app_number] => 16/837214 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16774191 [patent_doc_number] => 10985315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Resistive random-access memory [patent_app_type] => utility [patent_app_number] => 16/835843 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11014 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16835843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17130411 [patent_doc_number] => 20210305180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/833330 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17113619 [patent_doc_number] => 20210294216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => LITHOGRAPHY PROCESS WINDOW ENHANCEMENT FOR PHOTORESIST PATTERNING [patent_app_type] => utility [patent_app_number] => 16/825393 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17115565 [patent_doc_number] => 20210296162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => ENLARGING CONTACT AREA AND PROCESS WINDOW FOR A CONTACT VIA [patent_app_type] => utility [patent_app_number] => 16/822383 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16822383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16119759 [patent_doc_number] => 20200211902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => GATE STACK OPTIMIZATION FOR WIDE AND NARROW NANOSHEET TRANSISTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/815627 [patent_app_country] => US [patent_app_date] => 2020-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16815627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16635159 [patent_doc_number] => 10913654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Packaging a sealed cavity in an electronic device [patent_app_type] => utility [patent_app_number] => 16/813967 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3656 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16400519 [patent_doc_number] => 20200341377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => COMPOSITION FOR FORMING SILICON-CONTAINING RESIST UNDERLAYER FILM AND PATTERNING PROCESS [patent_app_type] => utility [patent_app_number] => 16/808664 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808664 [rel_patent_id] =>[rel_patent_doc_number] =>)