
Caleen O. Sullivan
Examiner (ID: 789, Phone: (571)272-6569 , Office: P/2896 )
| Most Active Art Unit | 2899 |
| Art Unit(s) | 2896, 1795, 1722, 2899, 1756 |
| Total Applications | 1358 |
| Issued Applications | 1151 |
| Pending Applications | 77 |
| Abandoned Applications | 165 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19130831
[patent_doc_number] => 20240136184
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-25
[patent_title] => METHOD FOR FORMING AND USING MASK
[patent_app_type] => utility
[patent_app_number] => 18/401800
[patent_app_country] => US
[patent_app_date] => 2024-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6749
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401800
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/401800 | Method for forming and using mask | Jan 1, 2024 | Issued |
Array
(
[id] => 19924387
[patent_doc_number] => 12298667
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Lithography
[patent_app_type] => utility
[patent_app_number] => 18/398152
[patent_app_country] => US
[patent_app_date] => 2023-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 3045
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18398152
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/398152 | Lithography | Dec 27, 2023 | Issued |
Array
(
[id] => 19174125
[patent_doc_number] => 20240160099
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => METHODS FOR INCREASING THE DENSITY OF HIGH-INDEX NANOIMPRINT LITHOGRAPHY FILMS
[patent_app_type] => utility
[patent_app_number] => 18/394133
[patent_app_country] => US
[patent_app_date] => 2023-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11328
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18394133
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/394133 | Methods for increasing the density of high-index nanoimprint lithography films | Dec 21, 2023 | Issued |
Array
(
[id] => 19100972
[patent_doc_number] => 20240120200
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-11
[patent_title] => METHOD AND STRUCTURE OF CUT END WITH SELF-ALIGNED DOUBLE PATTERNING
[patent_app_type] => utility
[patent_app_number] => 18/543432
[patent_app_country] => US
[patent_app_date] => 2023-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6986
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543432
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/543432 | Method and structure of cut end with self-aligned double patterning | Dec 17, 2023 | Issued |
Array
(
[id] => 19057022
[patent_doc_number] => 20240098991
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => INPUT AND OUTPUT BLOCKS FOR AN ARRAY OF MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 18/520526
[patent_app_country] => US
[patent_app_date] => 2023-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14717
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520526
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/520526 | Input and output blocks for an array of memory cells | Nov 26, 2023 | Issued |
Array
(
[id] => 19888433
[patent_doc_number] => 12274183
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-08
[patent_title] => Memory cell with top electrode via
[patent_app_type] => utility
[patent_app_number] => 18/511133
[patent_app_country] => US
[patent_app_date] => 2023-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 32
[patent_no_of_words] => 11512
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511133
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/511133 | Memory cell with top electrode via | Nov 15, 2023 | Issued |
Array
(
[id] => 19038134
[patent_doc_number] => 20240087949
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => ENLARGING CONTACT AREA AND PROCESS WINDOW FOR A CONTACT VIA
[patent_app_type] => utility
[patent_app_number] => 18/511102
[patent_app_country] => US
[patent_app_date] => 2023-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14472
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511102
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/511102 | Enlarging contact area and process window for a contact via | Nov 15, 2023 | Issued |
Array
(
[id] => 19721940
[patent_doc_number] => 12207498
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-21
[patent_title] => Method for preparing pixel define layer
[patent_app_type] => utility
[patent_app_number] => 18/505596
[patent_app_country] => US
[patent_app_date] => 2023-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10939
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 962
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505596
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/505596 | Method for preparing pixel define layer | Nov 8, 2023 | Issued |
Array
(
[id] => 19008057
[patent_doc_number] => 20240072128
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => Sacrificial Layer for Semiconductor Process
[patent_app_type] => utility
[patent_app_number] => 18/502183
[patent_app_country] => US
[patent_app_date] => 2023-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9195
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502183
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/502183 | Sacrificial layer for semiconductor process | Nov 5, 2023 | Issued |
Array
(
[id] => 19442704
[patent_doc_number] => 12092962
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-09-17
[patent_title] => Measurements of structures in presence of signal contaminations
[patent_app_type] => utility
[patent_app_number] => 18/495247
[patent_app_country] => US
[patent_app_date] => 2023-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 10093
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18495247
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/495247 | Measurements of structures in presence of signal contaminations | Oct 25, 2023 | Issued |
Array
(
[id] => 20318093
[patent_doc_number] => 12456648
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-28
[patent_title] => Vertical semiconductor device and method for fabricating the same
[patent_app_type] => utility
[patent_app_number] => 18/461425
[patent_app_country] => US
[patent_app_date] => 2023-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 2436
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18461425
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/461425 | Vertical semiconductor device and method for fabricating the same | Sep 4, 2023 | Issued |
Array
(
[id] => 19428443
[patent_doc_number] => 12087881
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Trichrome pixel layout
[patent_app_type] => utility
[patent_app_number] => 18/455032
[patent_app_country] => US
[patent_app_date] => 2023-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 11934
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455032
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/455032 | Trichrome pixel layout | Aug 23, 2023 | Issued |
Array
(
[id] => 19428159
[patent_doc_number] => 12087592
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Ambient controlled two-step thermal treatment for spin-on coating layer planarization
[patent_app_type] => utility
[patent_app_number] => 18/446416
[patent_app_country] => US
[patent_app_date] => 2023-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6864
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446416
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/446416 | Ambient controlled two-step thermal treatment for spin-on coating layer planarization | Aug 7, 2023 | Issued |
Array
(
[id] => 18787587
[patent_doc_number] => 20230375920
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/230062
[patent_app_country] => US
[patent_app_date] => 2023-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10888
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230062
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/230062 | Method of manufacturing a semiconductor device | Aug 2, 2023 | Issued |
Array
(
[id] => 19341513
[patent_doc_number] => 12051711
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-30
[patent_title] => Anti-flare semiconductor packages and related methods
[patent_app_type] => utility
[patent_app_number] => 18/363289
[patent_app_country] => US
[patent_app_date] => 2023-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3723
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363289
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/363289 | Anti-flare semiconductor packages and related methods | Jul 31, 2023 | Issued |
Array
(
[id] => 19487376
[patent_doc_number] => 12107102
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-01
[patent_title] => Anti-flare semiconductor packages and related methods
[patent_app_type] => utility
[patent_app_number] => 18/363296
[patent_app_country] => US
[patent_app_date] => 2023-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3723
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363296
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/363296 | Anti-flare semiconductor packages and related methods | Jul 31, 2023 | Issued |
Array
(
[id] => 19426433
[patent_doc_number] => 12085843
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Method of manufacturing EUV photo masks
[patent_app_type] => utility
[patent_app_number] => 18/226151
[patent_app_country] => US
[patent_app_date] => 2023-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 22
[patent_no_of_words] => 7151
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226151
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/226151 | Method of manufacturing EUV photo masks | Jul 24, 2023 | Issued |
Array
(
[id] => 19228050
[patent_doc_number] => 12007684
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-11
[patent_title] => Mask blank, method of manufacturing imprint mold, method of manufacturing transfer mask, method of manufacturing reflective mask, and method of manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/226165
[patent_app_country] => US
[patent_app_date] => 2023-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 22
[patent_no_of_words] => 17788
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226165
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/226165 | Mask blank, method of manufacturing imprint mold, method of manufacturing transfer mask, method of manufacturing reflective mask, and method of manufacturing semiconductor device | Jul 24, 2023 | Issued |
Array
(
[id] => 18776423
[patent_doc_number] => 20230371261
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => PERIPHERAL CIRCUITRY UNDER ARRAY MEMORY DEVICE AND METHOD OF FABRICATING THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/358365
[patent_app_country] => US
[patent_app_date] => 2023-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8541
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358365
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/358365 | Peripheral circuitry under array memory device and method of fabricating thereof | Jul 24, 2023 | Issued |
Array
(
[id] => 19428298
[patent_doc_number] => 12087732
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Isolation bonding film for semiconductor packages and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 18/338013
[patent_app_country] => US
[patent_app_date] => 2023-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 7562
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338013
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/338013 | Isolation bonding film for semiconductor packages and methods of forming the same | Jun 19, 2023 | Issued |