
Caleen O. Sullivan
Examiner (ID: 789, Phone: (571)272-6569 , Office: P/2896 )
| Most Active Art Unit | 2899 |
| Art Unit(s) | 2896, 1795, 1722, 2899, 1756 |
| Total Applications | 1358 |
| Issued Applications | 1151 |
| Pending Applications | 77 |
| Abandoned Applications | 165 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13740457
[patent_doc_number] => 20180374698
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-27
[patent_title] => SEMICONDUCTOR TRANSISTOR HAVING SUPERLATTICE STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 16/060612
[patent_app_country] => US
[patent_app_date] => 2016-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3350
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16060612
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/060612 | Semiconductor transistor having superlattice structures | Oct 18, 2016 | Issued |
Array
(
[id] => 12595815
[patent_doc_number] => 20180090435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-29
[patent_title] => CONTACT TRENCH BETWEEN STACKED SEMICONDUCTOR SUBSTRATES
[patent_app_type] => utility
[patent_app_number] => 15/275619
[patent_app_country] => US
[patent_app_date] => 2016-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2765
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275619
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/275619 | Contact trench between stacked semiconductor substrates | Sep 25, 2016 | Issued |
Array
(
[id] => 12584391
[patent_doc_number] => 20180086626
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-29
[patent_title] => METHOD OF MANUFACTURING A SENSOR
[patent_app_type] => utility
[patent_app_number] => 15/275662
[patent_app_country] => US
[patent_app_date] => 2016-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3817
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275662
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/275662 | Method of manufacturing a sensor | Sep 25, 2016 | Issued |
Array
(
[id] => 11967069
[patent_doc_number] => 20170271222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-21
[patent_title] => 'ELECTRONIC ELEMENT PACKAGE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/275603
[patent_app_country] => US
[patent_app_date] => 2016-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7045
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275603
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/275603 | Electronic element package and method for manufacturing the same | Sep 25, 2016 | Issued |
Array
(
[id] => 12314757
[patent_doc_number] => 09941305
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-10
[patent_title] => Pixel structure and fabrication method thereof
[patent_app_type] => utility
[patent_app_number] => 15/275564
[patent_app_country] => US
[patent_app_date] => 2016-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 46
[patent_no_of_words] => 9641
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275564
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/275564 | Pixel structure and fabrication method thereof | Sep 25, 2016 | Issued |
Array
(
[id] => 11890775
[patent_doc_number] => 09761340
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-12
[patent_title] => 'Method of preparing strain released strip-bent x-ray crystal analyzers'
[patent_app_type] => utility
[patent_app_number] => 15/275430
[patent_app_country] => US
[patent_app_date] => 2016-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 1117
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275430
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/275430 | Method of preparing strain released strip-bent x-ray crystal analyzers | Sep 24, 2016 | Issued |
Array
(
[id] => 11592742
[patent_doc_number] => 20170117154
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-27
[patent_title] => 'SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/275111
[patent_app_country] => US
[patent_app_date] => 2016-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7321
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275111
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/275111 | Semiconductor structures and fabrication method thereof | Sep 22, 2016 | Issued |
Array
(
[id] => 12354945
[patent_doc_number] => 09953827
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-24
[patent_title] => Method of forming semiconductor device having dielectric layer and related system
[patent_app_type] => utility
[patent_app_number] => 15/273797
[patent_app_country] => US
[patent_app_date] => 2016-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 6291
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273797
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/273797 | Method of forming semiconductor device having dielectric layer and related system | Sep 22, 2016 | Issued |
Array
(
[id] => 12595683
[patent_doc_number] => 20180090391
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-29
[patent_title] => METHODS, APPARATUS AND SYSTEM FOR SELF-ALIGNED RETROGRADE WELL DOPING FOR FINFET DEVICES
[patent_app_type] => utility
[patent_app_number] => 15/274974
[patent_app_country] => US
[patent_app_date] => 2016-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4967
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15274974
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/274974 | Methods, apparatus and system for self-aligned retrograde well doping for finFET devices | Sep 22, 2016 | Issued |
Array
(
[id] => 12574245
[patent_doc_number] => 10020343
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-10
[patent_title] => Wafer-level back-end fabrication systems and methods
[patent_app_type] => utility
[patent_app_number] => 15/275134
[patent_app_country] => US
[patent_app_date] => 2016-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 34
[patent_no_of_words] => 4498
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275134
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/275134 | Wafer-level back-end fabrication systems and methods | Sep 22, 2016 | Issued |
Array
(
[id] => 11517591
[patent_doc_number] => 20170084665
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-23
[patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/275057
[patent_app_country] => US
[patent_app_date] => 2016-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 4101
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275057
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/275057 | Method of manufacturing a semiconductor device | Sep 22, 2016 | Issued |
Array
(
[id] => 13019027
[patent_doc_number] => 10032629
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-24
[patent_title] => Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
[patent_app_type] => utility
[patent_app_number] => 15/274140
[patent_app_country] => US
[patent_app_date] => 2016-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 13753
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15274140
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/274140 | Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium | Sep 22, 2016 | Issued |
Array
(
[id] => 11532525
[patent_doc_number] => 20170092503
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-30
[patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/273780
[patent_app_country] => US
[patent_app_date] => 2016-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 17250
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273780
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/273780 | Method of manufacturing a semiconductor device | Sep 22, 2016 | Issued |
Array
(
[id] => 13653253
[patent_doc_number] => 09852947
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-12-26
[patent_title] => Forming sidewall spacers using isotropic etch
[patent_app_type] => utility
[patent_app_number] => 15/271318
[patent_app_country] => US
[patent_app_date] => 2016-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 4729
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15271318
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/271318 | Forming sidewall spacers using isotropic etch | Sep 20, 2016 | Issued |
Array
(
[id] => 13173821
[patent_doc_number] => 10103032
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-16
[patent_title] => Methods of forming etch masks for sub-resolution substrate patterning
[patent_app_type] => utility
[patent_app_number] => 15/271876
[patent_app_country] => US
[patent_app_date] => 2016-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 31
[patent_no_of_words] => 6439
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15271876
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/271876 | Methods of forming etch masks for sub-resolution substrate patterning | Sep 20, 2016 | Issued |
Array
(
[id] => 11532669
[patent_doc_number] => 20170092647
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-30
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 15/271962
[patent_app_country] => US
[patent_app_date] => 2016-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 14117
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15271962
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/271962 | Method of manufacturing semiconductor device and non-transitory computer-readable recording medium | Sep 20, 2016 | Issued |
Array
(
[id] => 11532553
[patent_doc_number] => 20170092530
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-30
[patent_title] => 'SUBSTRATE HOLDING/ROTATING DEVICE, SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME, AND SUBSTRATE PROCESSING METHOD'
[patent_app_type] => utility
[patent_app_number] => 15/271642
[patent_app_country] => US
[patent_app_date] => 2016-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 21051
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15271642
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/271642 | Substrate holding/rotating device, substrate processing apparatus including the same, and substrate processing method | Sep 20, 2016 | Issued |
Array
(
[id] => 11918354
[patent_doc_number] => 09786545
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-10-10
[patent_title] => 'Method of forming ANA regions in an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 15/271519
[patent_app_country] => US
[patent_app_date] => 2016-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 23
[patent_no_of_words] => 5170
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15271519
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/271519 | Method of forming ANA regions in an integrated circuit | Sep 20, 2016 | Issued |
Array
(
[id] => 12174828
[patent_doc_number] => 09892977
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-13
[patent_title] => 'FinFET and method of forming fin of the FinFET'
[patent_app_type] => utility
[patent_app_number] => 15/270502
[patent_app_country] => US
[patent_app_date] => 2016-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 22
[patent_no_of_words] => 7834
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270502
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/270502 | FinFET and method of forming fin of the FinFET | Sep 19, 2016 | Issued |
Array
(
[id] => 12260759
[patent_doc_number] => 20180079955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-22
[patent_title] => 'METHODS FOR FABRICATING DEVICES CONTAINING RED LINE EMITTING PHOSPHORS'
[patent_app_type] => utility
[patent_app_number] => 15/270657
[patent_app_country] => US
[patent_app_date] => 2016-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 7474
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270657
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/270657 | Methods for fabricating devices containing red line emitting phosphors | Sep 19, 2016 | Issued |