Search

Caleen O. Sullivan

Examiner (ID: 789, Phone: (571)272-6569 , Office: P/2896 )

Most Active Art Unit
2899
Art Unit(s)
2896, 1795, 1722, 2899, 1756
Total Applications
1358
Issued Applications
1151
Pending Applications
77
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11532527 [patent_doc_number] => 20170092506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'Methods of Forming Etch Masks for Sub-Resolution Substrate Patterning' [patent_app_type] => utility [patent_app_number] => 15/270841 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270841 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270841
Methods of forming etch masks for sub-resolution substrate patterning Sep 19, 2016 Issued
Array ( [id] => 16133047 [patent_doc_number] => 10700295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Metal complexes [patent_app_type] => utility [patent_app_number] => 15/760037 [patent_app_country] => US [patent_app_date] => 2016-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 27 [patent_no_of_words] => 28166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15760037 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/760037
Metal complexes Sep 8, 2016 Issued
Array ( [id] => 13682373 [patent_doc_number] => 20160379923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => INTEGRATED CIRCUIT PACKAGE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/260099 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15260099 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/260099
Integrated circuit package substrate Sep 7, 2016 Issued
Array ( [id] => 13085109 [patent_doc_number] => 10062627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/252158 [patent_app_country] => US [patent_app_date] => 2016-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3796 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15252158 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/252158
Semiconductor device Aug 29, 2016 Issued
Array ( [id] => 13785731 [patent_doc_number] => 20190006404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => PACKAGING STRUCTURE AND PACKAGING METHOD [patent_app_type] => utility [patent_app_number] => 15/748651 [patent_app_country] => US [patent_app_date] => 2016-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15748651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/748651
Packaging structure and packaging method Aug 4, 2016 Issued
Array ( [id] => 12162387 [patent_doc_number] => 20180033653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'PROCESSING APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/220461 [patent_app_country] => US [patent_app_date] => 2016-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6903 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15220461 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/220461
Processing apparatus and method Jul 26, 2016 Issued
Array ( [id] => 11424839 [patent_doc_number] => 20170032985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'WAFER PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 15/219499 [patent_app_country] => US [patent_app_date] => 2016-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5610 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15219499 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/219499
Wafer processing method Jul 25, 2016 Issued
Array ( [id] => 11911123 [patent_doc_number] => 09779942 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-03 [patent_title] => 'Method of forming patterned mask layer' [patent_app_type] => utility [patent_app_number] => 15/220386 [patent_app_country] => US [patent_app_date] => 2016-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3468 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15220386 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/220386
Method of forming patterned mask layer Jul 25, 2016 Issued
Array ( [id] => 11459988 [patent_doc_number] => 20170053894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'METHOD FOR MANUFACTURING STRETCHABLE WIRE AND METHOD FOR MANUFACTURING STRETCHABLE INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/220145 [patent_app_country] => US [patent_app_date] => 2016-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5621 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15220145 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/220145
Method for manufacturing stretchable wire and method for manufacturing stretchable integrated circuit Jul 25, 2016 Issued
Array ( [id] => 11847562 [patent_doc_number] => 09735119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-15 [patent_title] => 'Conductive pads forming method' [patent_app_type] => utility [patent_app_number] => 15/219265 [patent_app_country] => US [patent_app_date] => 2016-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 4840 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15219265 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/219265
Conductive pads forming method Jul 24, 2016 Issued
Array ( [id] => 14920523 [patent_doc_number] => 10431589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Memory cell, semiconductor integrated circuit device, and method for manufacturing semiconductor integrated circuit device [patent_app_type] => utility [patent_app_number] => 15/744163 [patent_app_country] => US [patent_app_date] => 2016-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 32150 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15744163 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/744163
Memory cell, semiconductor integrated circuit device, and method for manufacturing semiconductor integrated circuit device Jul 20, 2016 Issued
Array ( [id] => 17239699 [patent_doc_number] => 11183592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Field effect transistor with a hybrid gate spacer including a low-k dielectric material [patent_app_type] => utility [patent_app_number] => 16/306890 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 10803 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16306890 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/306890
Field effect transistor with a hybrid gate spacer including a low-k dielectric material Jun 30, 2016 Issued
Array ( [id] => 15045421 [patent_doc_number] => 20190333715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => METHOD OF MAKING AN ENERGY STORAGE ARTICLE [patent_app_type] => utility [patent_app_number] => 16/312696 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16312696 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/312696
Method of making an energy storage article Jun 23, 2016 Issued
Array ( [id] => 11551760 [patent_doc_number] => 09620622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Replacement metal gate dielectric cap' [patent_app_type] => utility [patent_app_number] => 15/189579 [patent_app_country] => US [patent_app_date] => 2016-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8433 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15189579 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/189579
Replacement metal gate dielectric cap Jun 21, 2016 Issued
Array ( [id] => 11687480 [patent_doc_number] => 09685530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Replacement metal gate dielectric cap' [patent_app_type] => utility [patent_app_number] => 15/182726 [patent_app_country] => US [patent_app_date] => 2016-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8433 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182726 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/182726
Replacement metal gate dielectric cap Jun 14, 2016 Issued
Array ( [id] => 12823336 [patent_doc_number] => 20180166284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => METHOD FOR MANUFACTURING BUMP STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/735219 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15735219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/735219
Method for manufacturing bump structure Jun 8, 2016 Issued
Array ( [id] => 11847583 [patent_doc_number] => 09735140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Systems and methods for a sequential spacer scheme' [patent_app_type] => utility [patent_app_number] => 15/173840 [patent_app_country] => US [patent_app_date] => 2016-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 34 [patent_no_of_words] => 4982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15173840 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/173840
Systems and methods for a sequential spacer scheme Jun 5, 2016 Issued
Array ( [id] => 11898138 [patent_doc_number] => 09768077 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-19 [patent_title] => 'Low resistance dual liner contacts for Fin Field-Effect Transistors (FinFETs)' [patent_app_type] => utility [patent_app_number] => 15/171486 [patent_app_country] => US [patent_app_date] => 2016-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5258 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15171486 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/171486
Low resistance dual liner contacts for Fin Field-Effect Transistors (FinFETs) Jun 1, 2016 Issued
Array ( [id] => 12095663 [patent_doc_number] => 20170352756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MAKING' [patent_app_type] => utility [patent_app_number] => 15/171047 [patent_app_country] => US [patent_app_date] => 2016-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15171047 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/171047
Semiconductor device and method of making Jun 1, 2016 Issued
Array ( [id] => 12109215 [patent_doc_number] => 09865705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Vertical field effect transistors with bottom source/drain epitaxy' [patent_app_type] => utility [patent_app_number] => 15/171040 [patent_app_country] => US [patent_app_date] => 2016-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15171040 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/171040
Vertical field effect transistors with bottom source/drain epitaxy Jun 1, 2016 Issued
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