Search

Caleen O. Sullivan

Examiner (ID: 789, Phone: (571)272-6569 , Office: P/2896 )

Most Active Art Unit
2899
Art Unit(s)
2896, 1795, 1722, 2899, 1756
Total Applications
1358
Issued Applications
1151
Pending Applications
77
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9849989 [patent_doc_number] => 08951715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Method of forming patterned film on a bottom and a top-surface of a deep trench' [patent_app_type] => utility [patent_app_number] => 14/082758 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2714 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082758 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082758
Method of forming patterned film on a bottom and a top-surface of a deep trench Nov 17, 2013 Issued
Array ( [id] => 10617631 [patent_doc_number] => 09337080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Method for manufacturing SOI wafer' [patent_app_type] => utility [patent_app_number] => 14/428700 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6832 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14428700 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/428700
Method for manufacturing SOI wafer Nov 6, 2013 Issued
Array ( [id] => 10010518 [patent_doc_number] => 09054043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Method for directed self-assembly (DSA) of block copolymers' [patent_app_type] => utility [patent_app_number] => 14/067769 [patent_app_country] => US [patent_app_date] => 2013-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 32 [patent_no_of_words] => 6533 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14067769 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/067769
Method for directed self-assembly (DSA) of block copolymers Oct 29, 2013 Issued
Array ( [id] => 11360385 [patent_doc_number] => 09537044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Optoelectric device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/438188 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 10613 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14438188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/438188
Optoelectric device and method for manufacturing the same Oct 22, 2013 Issued
Array ( [id] => 9817417 [patent_doc_number] => 08927200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Double patterning method' [patent_app_type] => utility [patent_app_number] => 14/059596 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 13 [patent_no_of_words] => 15036 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059596 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/059596
Double patterning method Oct 21, 2013 Issued
Array ( [id] => 10433224 [patent_doc_number] => 20150318236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/368721 [patent_app_country] => US [patent_app_date] => 2013-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6597 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14368721 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/368721
Integrated circuit package substrate Oct 15, 2013 Issued
Array ( [id] => 9408328 [patent_doc_number] => 20140099580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'SPATIAL AND TEMPORAL CONTROL OF BRUSH FORMATION ON SURFACES' [patent_app_type] => utility [patent_app_number] => 14/050098 [patent_app_country] => US [patent_app_date] => 2013-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12750 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050098 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/050098
Spatial and temporal control of brush formation on surfaces Oct 8, 2013 Issued
Array ( [id] => 11483379 [patent_doc_number] => 09589934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Method for interconnecting stacked semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/368774 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14368774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/368774
Method for interconnecting stacked semiconductor devices Sep 26, 2013 Issued
Array ( [id] => 11483379 [patent_doc_number] => 09589934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Method for interconnecting stacked semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/368774 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14368774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/368774
Method for interconnecting stacked semiconductor devices Sep 26, 2013 Issued
Array ( [id] => 11483379 [patent_doc_number] => 09589934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Method for interconnecting stacked semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/368774 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14368774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/368774
Method for interconnecting stacked semiconductor devices Sep 26, 2013 Issued
Array ( [id] => 11483379 [patent_doc_number] => 09589934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Method for interconnecting stacked semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/368774 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14368774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/368774
Method for interconnecting stacked semiconductor devices Sep 26, 2013 Issued
Array ( [id] => 11483379 [patent_doc_number] => 09589934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Method for interconnecting stacked semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/368774 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14368774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/368774
Method for interconnecting stacked semiconductor devices Sep 26, 2013 Issued
Array ( [id] => 11925571 [patent_doc_number] => 09793159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects' [patent_app_type] => utility [patent_app_number] => 14/911991 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9479 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14911991 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/911991
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects Sep 26, 2013 Issued
Array ( [id] => 11925575 [patent_doc_number] => 09793163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects' [patent_app_type] => utility [patent_app_number] => 14/912036 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 8193 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14912036 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/912036
Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects Sep 26, 2013 Issued
Array ( [id] => 11483379 [patent_doc_number] => 09589934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Method for interconnecting stacked semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/368774 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14368774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/368774
Method for interconnecting stacked semiconductor devices Sep 26, 2013 Issued
Array ( [id] => 9280692 [patent_doc_number] => 20140030660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'MULTILAYER RESIST PROCESS PATTERN-FORMING METHOD AND MULTILAYER RESIST PROCESS INORGANIC FILM-FORMING COMPOSITION' [patent_app_type] => utility [patent_app_number] => 14/038861 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23632 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14038861 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/038861
Multilayer resist process pattern-forming method and multilayer resist process inorganic film-forming composition Sep 26, 2013 Issued
Array ( [id] => 11483379 [patent_doc_number] => 09589934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Method for interconnecting stacked semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/368774 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14368774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/368774
Method for interconnecting stacked semiconductor devices Sep 26, 2013 Issued
Array ( [id] => 11483379 [patent_doc_number] => 09589934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Method for interconnecting stacked semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/368774 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14368774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/368774
Method for interconnecting stacked semiconductor devices Sep 26, 2013 Issued
Array ( [id] => 11483379 [patent_doc_number] => 09589934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Method for interconnecting stacked semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/368774 [patent_app_country] => US [patent_app_date] => 2013-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14368774 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/368774
Method for interconnecting stacked semiconductor devices Sep 26, 2013 Issued
Array ( [id] => 11811453 [patent_doc_number] => 09716026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Resin composition, cured film, laminated film, and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/430361 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10944 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14430361 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/430361
Resin composition, cured film, laminated film, and method for manufacturing semiconductor device Sep 24, 2013 Issued
Menu