Search

Caleen O. Sullivan

Examiner (ID: 789, Phone: (571)272-6569 , Office: P/2896 )

Most Active Art Unit
2899
Art Unit(s)
2896, 1795, 1722, 2899, 1756
Total Applications
1358
Issued Applications
1151
Pending Applications
77
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8305643 [patent_doc_number] => 08227176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Method for forming fine pattern in semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/165401 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 1704 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12165401 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165401
Method for forming fine pattern in semiconductor device Jun 29, 2008 Issued
Array ( [id] => 4562904 [patent_doc_number] => 07846641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Glass substrate having circuit pattern and process for producing the same' [patent_app_type] => utility [patent_app_number] => 12/143446 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 10221 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/846/07846641.pdf [firstpage_image] =>[orig_patent_app_number] => 12143446 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/143446
Glass substrate having circuit pattern and process for producing the same Jun 19, 2008 Issued
Array ( [id] => 6229516 [patent_doc_number] => 20100183983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'PROCESS FOR MANUFACTURING ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 12/665175 [patent_app_country] => US [patent_app_date] => 2008-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8039 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20100183983.pdf [firstpage_image] =>[orig_patent_app_number] => 12665175 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/665175
PROCESS FOR MANUFACTURING ELECTRONIC DEVICE Jun 15, 2008 Abandoned
Array ( [id] => 7545204 [patent_doc_number] => 08053175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Method of forming measuring targets for measuring dimensions of substrate in substrate manufacturing process' [patent_app_type] => utility [patent_app_number] => 12/136292 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3370 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/053/08053175.pdf [firstpage_image] =>[orig_patent_app_number] => 12136292 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136292
Method of forming measuring targets for measuring dimensions of substrate in substrate manufacturing process Jun 9, 2008 Issued
Array ( [id] => 5409976 [patent_doc_number] => 20090123875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR PROCESSING ETCHING-TARGET FILM' [patent_app_type] => utility [patent_app_number] => 12/134492 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9298 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20090123875.pdf [firstpage_image] =>[orig_patent_app_number] => 12134492 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/134492
Method for manufacturing semiconductor device, and method for processing etching-target film Jun 5, 2008 Issued
Array ( [id] => 5264810 [patent_doc_number] => 20090117495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'METHOD FOR FORMING A PATTERN IN A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/119926 [patent_app_country] => US [patent_app_date] => 2008-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2281 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20090117495.pdf [firstpage_image] =>[orig_patent_app_number] => 12119926 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/119926
METHOD FOR FORMING A PATTERN IN A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A FLASH MEMORY DEVICE May 12, 2008 Abandoned
Array ( [id] => 5564021 [patent_doc_number] => 20090136874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'Method for manufacturing printed circuit board' [patent_app_type] => utility [patent_app_number] => 12/149750 [patent_app_country] => US [patent_app_date] => 2008-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1958 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20090136874.pdf [firstpage_image] =>[orig_patent_app_number] => 12149750 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/149750
Method for manufacturing printed circuit board May 6, 2008 Abandoned
Array ( [id] => 5485217 [patent_doc_number] => 20090274982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'METHOD OF MAKING A SEMICONDUCTOR DEVICE USING NEGATIVE PHOTORESIST' [patent_app_type] => utility [patent_app_number] => 12/112058 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20090274982.pdf [firstpage_image] =>[orig_patent_app_number] => 12112058 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112058
Method of making a semiconductor device using negative photoresist Apr 29, 2008 Issued
Array ( [id] => 4957488 [patent_doc_number] => 20080271912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/110606 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11614 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20080271912.pdf [firstpage_image] =>[orig_patent_app_number] => 12110606 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/110606
PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF Apr 27, 2008 Abandoned
Array ( [id] => 5495723 [patent_doc_number] => 20090263751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'Methods for double patterning photoresist' [patent_app_type] => utility [patent_app_number] => 12/148826 [patent_app_country] => US [patent_app_date] => 2008-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20090263751.pdf [firstpage_image] =>[orig_patent_app_number] => 12148826 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/148826
Methods for double patterning photoresist Apr 21, 2008 Abandoned
Array ( [id] => 5458170 [patent_doc_number] => 20090258322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'METHODS FOR PLANARIZING UNEVENNESS ON SURFACE OF WAFER PHOTORESIST LAYER AND WAFERS PRODUCED BY THE METHODS' [patent_app_type] => utility [patent_app_number] => 12/100716 [patent_app_country] => US [patent_app_date] => 2008-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4007 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20090258322.pdf [firstpage_image] =>[orig_patent_app_number] => 12100716 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/100716
Methods for planarizing unevenness on surface of wafer photoresist layer and wafers produced by the methods Apr 9, 2008 Issued
Array ( [id] => 5473540 [patent_doc_number] => 20090246706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'PATTERNING RESOLUTION ENHANCEMENT COMBINING INTERFERENCE LITHOGRAPHY AND SELF-ALIGNED DOUBLE PATTERNING TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 12/060612 [patent_app_country] => US [patent_app_date] => 2008-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9421 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20090246706.pdf [firstpage_image] =>[orig_patent_app_number] => 12060612 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/060612
PATTERNING RESOLUTION ENHANCEMENT COMBINING INTERFERENCE LITHOGRAPHY AND SELF-ALIGNED DOUBLE PATTERNING TECHNIQUES Mar 31, 2008 Abandoned
Array ( [id] => 4595366 [patent_doc_number] => 07981591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Semiconductor buried grating fabrication method' [patent_app_type] => utility [patent_app_number] => 12/079524 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3087 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/981/07981591.pdf [firstpage_image] =>[orig_patent_app_number] => 12079524 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/079524
Semiconductor buried grating fabrication method Mar 26, 2008 Issued
Array ( [id] => 4719235 [patent_doc_number] => 20080241757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Reproducible, high yield method for fabricating ultra-short T-gates on HFETs' [patent_app_type] => utility [patent_app_number] => 12/079529 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 988 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20080241757.pdf [firstpage_image] =>[orig_patent_app_number] => 12079529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/079529
Reproducible, high yield method for fabricating ultra-short T-gates on HFETs Mar 26, 2008 Issued
Array ( [id] => 4719237 [patent_doc_number] => 20080241759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'METHOD OF MANUFACTURING WIRING CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 12/055711 [patent_app_country] => US [patent_app_date] => 2008-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6126 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20080241759.pdf [firstpage_image] =>[orig_patent_app_number] => 12055711 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/055711
Method of manufacturing wiring circuit board Mar 25, 2008 Issued
Array ( [id] => 5545856 [patent_doc_number] => 20090155733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'METHOD OF FORMING ISO SPACE PATTERN' [patent_app_type] => utility [patent_app_number] => 12/050931 [patent_app_country] => US [patent_app_date] => 2008-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3366 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20090155733.pdf [firstpage_image] =>[orig_patent_app_number] => 12050931 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/050931
METHOD OF FORMING ISO SPACE PATTERN Mar 17, 2008 Abandoned
Array ( [id] => 5533448 [patent_doc_number] => 20090233236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'METHOD FOR FABRICATING SELF-ALIGNED NANOSTRUCTURE USING SELF-ASSEMBLY BLOCK COPOLYMERS, AND STRUCTURES FABRICATED THEREFROM' [patent_app_type] => utility [patent_app_number] => 12/049780 [patent_app_country] => US [patent_app_date] => 2008-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11257 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20090233236.pdf [firstpage_image] =>[orig_patent_app_number] => 12049780 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/049780
Method for fabricating self-aligned nanostructure using self-assembly block copolymers, and structures fabricated therefrom Mar 16, 2008 Issued
Array ( [id] => 4527630 [patent_doc_number] => 07923201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Near-field exposure method' [patent_app_type] => utility [patent_app_number] => 12/048767 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 5077 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/923/07923201.pdf [firstpage_image] =>[orig_patent_app_number] => 12048767 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/048767
Near-field exposure method Mar 13, 2008 Issued
Array ( [id] => 4624010 [patent_doc_number] => 08003305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Method for patterning a semiconductor wafer' [patent_app_type] => utility [patent_app_number] => 12/041500 [patent_app_country] => US [patent_app_date] => 2008-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 4583 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/003/08003305.pdf [firstpage_image] =>[orig_patent_app_number] => 12041500 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/041500
Method for patterning a semiconductor wafer Mar 2, 2008 Issued
Array ( [id] => 4739868 [patent_doc_number] => 20080233521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Method for manufacturing substrate for making microarray' [patent_app_type] => utility [patent_app_number] => 12/071889 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5612 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20080233521.pdf [firstpage_image] =>[orig_patent_app_number] => 12071889 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/071889
Method for manufacturing substrate for making microarray Feb 26, 2008 Issued
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