
Calvin E. Vansant
Examiner (ID: 11143, Phone: (571)272-5714 , Office: P/2915 )
| Most Active Art Unit | 2915 |
| Art Unit(s) | 2937, 2961, 2915 |
| Total Applications | 1582 |
| Issued Applications | 1536 |
| Pending Applications | 8 |
| Abandoned Applications | 37 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10741501
[patent_doc_number] => 20160087651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-24
[patent_title] => 'SYSTEM AND METHOD FOR DECODING VARIABLE LENGTH CODES'
[patent_app_type] => utility
[patent_app_number] => 14/836900
[patent_app_country] => US
[patent_app_date] => 2015-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8362
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14836900
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/836900 | System and method for decoding variable length codes | Aug 25, 2015 | Issued |
Array
(
[id] => 12474717
[patent_doc_number] => 09990157
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-05
[patent_title] => Parity stripe lock engine
[patent_app_type] => utility
[patent_app_number] => 14/833694
[patent_app_country] => US
[patent_app_date] => 2015-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 10391
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 302
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833694
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/833694 | Parity stripe lock engine | Aug 23, 2015 | Issued |
Array
(
[id] => 11645986
[patent_doc_number] => 09667387
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-30
[patent_title] => 'IC card, portable electronic device, and IC card processing device'
[patent_app_type] => utility
[patent_app_number] => 14/833944
[patent_app_country] => US
[patent_app_date] => 2015-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 7578
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833944
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/833944 | IC card, portable electronic device, and IC card processing device | Aug 23, 2015 | Issued |
Array
(
[id] => 13361259
[patent_doc_number] => 20180232169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-16
[patent_title] => SOLID STATE STORAGE DEVICE WITH QUICK BOOT FROM NAND MEDIA
[patent_app_type] => utility
[patent_app_number] => 15/749402
[patent_app_country] => US
[patent_app_date] => 2015-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4056
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15749402
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/749402 | Solid state storage device with quick boot from NAND media | Aug 19, 2015 | Issued |
Array
(
[id] => 11232733
[patent_doc_number] => 09459960
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-10-04
[patent_title] => 'Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation'
[patent_app_type] => utility
[patent_app_number] => 14/830358
[patent_app_country] => US
[patent_app_date] => 2015-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 12150
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830358
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/830358 | Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation | Aug 18, 2015 | Issued |
Array
(
[id] => 11875386
[patent_doc_number] => 09747159
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-29
[patent_title] => 'MRAM smart bit write algorithm with error correction parity bits'
[patent_app_type] => utility
[patent_app_number] => 14/827591
[patent_app_country] => US
[patent_app_date] => 2015-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3774
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827591
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/827591 | MRAM smart bit write algorithm with error correction parity bits | Aug 16, 2015 | Issued |
Array
(
[id] => 10550267
[patent_doc_number] => 09274892
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-01
[patent_title] => 'Memory chip with error detection and retry modes of operation'
[patent_app_type] => utility
[patent_app_number] => 14/828013
[patent_app_country] => US
[patent_app_date] => 2015-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 12106
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828013
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/828013 | Memory chip with error detection and retry modes of operation | Aug 16, 2015 | Issued |
Array
(
[id] => 10493795
[patent_doc_number] => 20150378817
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-31
[patent_title] => 'Memory System With Error Detection And Retry Modes Of Operation'
[patent_app_type] => utility
[patent_app_number] => 14/827978
[patent_app_country] => US
[patent_app_date] => 2015-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 12108
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827978
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/827978 | Memory system with error detection and retry modes of operation | Aug 16, 2015 | Issued |
Array
(
[id] => 10464906
[patent_doc_number] => 20150349922
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-03
[patent_title] => 'METHOD AND SYSTEM FOR ERROR CORRECTION IN TRANSMITTING DATA USING LOW COMPLEXITY SYSTEMATIC ENCODER'
[patent_app_type] => utility
[patent_app_number] => 14/825399
[patent_app_country] => US
[patent_app_date] => 2015-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 11757
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14825399
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/825399 | Method and system for error correction in transmitting data using low complexity systematic encoder | Aug 12, 2015 | Issued |
Array
(
[id] => 10653689
[patent_doc_number] => 09369967
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-14
[patent_title] => 'Terminal apparatus and retransmission control method'
[patent_app_type] => utility
[patent_app_number] => 14/824808
[patent_app_country] => US
[patent_app_date] => 2015-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 16676
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14824808
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/824808 | Terminal apparatus and retransmission control method | Aug 11, 2015 | Issued |
Array
(
[id] => 11644893
[patent_doc_number] => 09666280
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-30
[patent_title] => 'Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage'
[patent_app_type] => utility
[patent_app_number] => 14/822680
[patent_app_country] => US
[patent_app_date] => 2015-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 21
[patent_no_of_words] => 18536
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14822680
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/822680 | Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage | Aug 9, 2015 | Issued |
Array
(
[id] => 13863659
[patent_doc_number] => 10193568
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-29
[patent_title] => Optical coherent receiver with forward error correction
[patent_app_type] => utility
[patent_app_number] => 15/515336
[patent_app_country] => US
[patent_app_date] => 2015-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 10139
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15515336
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/515336 | Optical coherent receiver with forward error correction | Aug 4, 2015 | Issued |
Array
(
[id] => 11700742
[patent_doc_number] => 09690659
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-27
[patent_title] => 'Parity-layout generating method, parity-layout generating apparatus, and storage system'
[patent_app_type] => utility
[patent_app_number] => 14/814564
[patent_app_country] => US
[patent_app_date] => 2015-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7430
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14814564
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/814564 | Parity-layout generating method, parity-layout generating apparatus, and storage system | Jul 30, 2015 | Issued |
Array
(
[id] => 11432900
[patent_doc_number] => 09571231
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-14
[patent_title] => 'In-band status encoding and decoding using error correction symbols'
[patent_app_type] => utility
[patent_app_number] => 14/814206
[patent_app_country] => US
[patent_app_date] => 2015-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6364
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14814206
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/814206 | In-band status encoding and decoding using error correction symbols | Jul 29, 2015 | Issued |
Array
(
[id] => 11700601
[patent_doc_number] => 09690516
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-27
[patent_title] => 'Parity stripe lock engine'
[patent_app_type] => utility
[patent_app_number] => 14/813286
[patent_app_country] => US
[patent_app_date] => 2015-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 10816
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14813286
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/813286 | Parity stripe lock engine | Jul 29, 2015 | Issued |
Array
(
[id] => 13171301
[patent_doc_number] => 10101763
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-16
[patent_title] => Interface adjustment processes for a data storage device
[patent_app_type] => utility
[patent_app_number] => 14/812794
[patent_app_country] => US
[patent_app_date] => 2015-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 18292
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14812794
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/812794 | Interface adjustment processes for a data storage device | Jul 28, 2015 | Issued |
Array
(
[id] => 11600506
[patent_doc_number] => 09647690
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-09
[patent_title] => 'Systems and methods for error correction coding'
[patent_app_type] => utility
[patent_app_number] => 14/806874
[patent_app_country] => US
[patent_app_date] => 2015-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 8517
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 315
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14806874
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/806874 | Systems and methods for error correction coding | Jul 22, 2015 | Issued |
Array
(
[id] => 12575655
[patent_doc_number] => 10020822
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-10
[patent_title] => Error tolerant memory system
[patent_app_type] => utility
[patent_app_number] => 15/323598
[patent_app_country] => US
[patent_app_date] => 2015-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5396
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15323598
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/323598 | Error tolerant memory system | Jul 19, 2015 | Issued |
Array
(
[id] => 10426991
[patent_doc_number] => 20150312002
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-29
[patent_title] => 'RECOVERY FROM BURST PACKET LOSS IN INTERNET PROTOCOL BASED WIRELESS NETWORKS USING STAGGERCASTING AND CROSS-PACKET FORWARD ERROR CORRECTION'
[patent_app_type] => utility
[patent_app_number] => 14/794900
[patent_app_country] => US
[patent_app_date] => 2015-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 10722
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794900
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/794900 | Recovery from burst packet loss in internet protocol based wireless networks using staggercasting and cross-packet forward error correction | Jul 8, 2015 | Issued |
Array
(
[id] => 11653627
[patent_doc_number] => 20170149532
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-25
[patent_title] => 'RECEIVING DEVICE, RECEIVING METHOD, AND COMPUTER PROGRAM'
[patent_app_type] => utility
[patent_app_number] => 15/323841
[patent_app_country] => US
[patent_app_date] => 2015-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8015
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15323841
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/323841 | Receiving device and receiving method | Jul 6, 2015 | Issued |