
Calvin E. Vansant
Examiner (ID: 11143, Phone: (571)272-5714 , Office: P/2915 )
| Most Active Art Unit | 2915 |
| Art Unit(s) | 2937, 2961, 2915 |
| Total Applications | 1582 |
| Issued Applications | 1536 |
| Pending Applications | 8 |
| Abandoned Applications | 37 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10092828
[patent_doc_number] => 09129654
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-09-08
[patent_title] => 'Systems and methods for data-path protection'
[patent_app_type] => utility
[patent_app_number] => 13/936426
[patent_app_country] => US
[patent_app_date] => 2013-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 22
[patent_no_of_words] => 10683
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13936426
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/936426 | Systems and methods for data-path protection | Jul 7, 2013 | Issued |
Array
(
[id] => 9133511
[patent_doc_number] => 20130294225
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-07
[patent_title] => 'Error Correction Coding Across Multiple Channels in Content Distribution Systems'
[patent_app_type] => utility
[patent_app_number] => 13/933734
[patent_app_country] => US
[patent_app_date] => 2013-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5751
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933734
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/933734 | Error correction coding across multiple channels in content distribution systems | Jul 1, 2013 | Issued |
Array
(
[id] => 10570943
[patent_doc_number] => 09294130
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-03-22
[patent_title] => 'Quasi-cyclic low-density parity-check (QC-LDPC) encoder'
[patent_app_type] => utility
[patent_app_number] => 13/924333
[patent_app_country] => US
[patent_app_date] => 2013-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3838
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13924333
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/924333 | Quasi-cyclic low-density parity-check (QC-LDPC) encoder | Jun 20, 2013 | Issued |
Array
(
[id] => 10036203
[patent_doc_number] => 09077534
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-07
[patent_title] => 'Communications circuit including a linear quadratic estimator'
[patent_app_type] => utility
[patent_app_number] => 13/923283
[patent_app_country] => US
[patent_app_date] => 2013-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 6466
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13923283
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/923283 | Communications circuit including a linear quadratic estimator | Jun 19, 2013 | Issued |
Array
(
[id] => 9308616
[patent_doc_number] => 20140047290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-13
[patent_title] => 'ERROR GENERATING APPARATUS FOR SOLID STATE DRIVE TESTER'
[patent_app_type] => utility
[patent_app_number] => 13/921949
[patent_app_country] => US
[patent_app_date] => 2013-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7833
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13921949
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/921949 | Error generating apparatus for solid state drive tester | Jun 18, 2013 | Issued |
Array
(
[id] => 10518560
[patent_doc_number] => 09245613
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-26
[patent_title] => 'Storage interface apparatus for solid state drive tester'
[patent_app_type] => utility
[patent_app_number] => 13/921829
[patent_app_country] => US
[patent_app_date] => 2013-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5092
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13921829
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/921829 | Storage interface apparatus for solid state drive tester | Jun 18, 2013 | Issued |
Array
(
[id] => 9308612
[patent_doc_number] => 20140047286
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-13
[patent_title] => 'SOLID STATE DRIVE TESTER'
[patent_app_type] => utility
[patent_app_number] => 13/921701
[patent_app_country] => US
[patent_app_date] => 2013-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3687
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13921701
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/921701 | Solid state drive tester | Jun 18, 2013 | Issued |
Array
(
[id] => 10589563
[patent_doc_number] => 09311180
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-12
[patent_title] => 'Semiconductor storage circuit and operation method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/921112
[patent_app_country] => US
[patent_app_date] => 2013-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8037
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 259
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13921112
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/921112 | Semiconductor storage circuit and operation method thereof | Jun 17, 2013 | Issued |
Array
(
[id] => 10969785
[patent_doc_number] => 20140372818
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-18
[patent_title] => 'Test-Per-Clock Based On Dynamically-Partitioned Reconfigurable Scan Chains'
[patent_app_type] => utility
[patent_app_number] => 13/919974
[patent_app_country] => US
[patent_app_date] => 2013-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3774
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13919974
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/919974 | Test-per-clock based on dynamically-partitioned reconfigurable scan chains | Jun 16, 2013 | Issued |
Array
(
[id] => 9954435
[patent_doc_number] => 09003248
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-07
[patent_title] => 'Fault-driven scan chain configuration for test-per-clock'
[patent_app_type] => utility
[patent_app_number] => 13/919998
[patent_app_country] => US
[patent_app_date] => 2013-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4568
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13919998
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/919998 | Fault-driven scan chain configuration for test-per-clock | Jun 16, 2013 | Issued |
Array
(
[id] => 10072470
[patent_doc_number] => 09110829
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-18
[patent_title] => 'MRAM smart bit write algorithm with error correction parity bits'
[patent_app_type] => utility
[patent_app_number] => 13/917772
[patent_app_country] => US
[patent_app_date] => 2013-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3632
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13917772
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/917772 | MRAM smart bit write algorithm with error correction parity bits | Jun 13, 2013 | Issued |
Array
(
[id] => 10969794
[patent_doc_number] => 20140372827
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-18
[patent_title] => 'PULSED-LATCH BASED RAZOR WITH 1-CYCLE ERROR RECOVERY SCHEME'
[patent_app_type] => utility
[patent_app_number] => 13/918587
[patent_app_country] => US
[patent_app_date] => 2013-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6332
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13918587
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/918587 | Pulsed-latch based razor with 1-cycle error recovery scheme | Jun 13, 2013 | Issued |
Array
(
[id] => 9109997
[patent_doc_number] => 20130283129
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-24
[patent_title] => 'SOLID-STATE MASS STORAGE DEVICE AND METHOD FOR FAILURE ANTICIPATION'
[patent_app_type] => utility
[patent_app_number] => 13/917773
[patent_app_country] => US
[patent_app_date] => 2013-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5267
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13917773
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/917773 | SOLID-STATE MASS STORAGE DEVICE AND METHOD FOR FAILURE ANTICIPATION | Jun 13, 2013 | Abandoned |
Array
(
[id] => 10507592
[patent_doc_number] => 09235466
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-12
[patent_title] => 'Memory devices with selective error correction code'
[patent_app_type] => utility
[patent_app_number] => 13/915179
[patent_app_country] => US
[patent_app_date] => 2013-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 28
[patent_no_of_words] => 19269
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13915179
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/915179 | Memory devices with selective error correction code | Jun 10, 2013 | Issued |
Array
(
[id] => 12325617
[patent_doc_number] => 09944520
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-17
[patent_title] => Syndrome of degraded quantum redundancy coded states
[patent_app_type] => utility
[patent_app_number] => 13/912876
[patent_app_country] => US
[patent_app_date] => 2013-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8484
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13912876
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/912876 | Syndrome of degraded quantum redundancy coded states | Jun 6, 2013 | Issued |
Array
(
[id] => 10582729
[patent_doc_number] => 09304854
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-05
[patent_title] => 'Semiconductor device and operating method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/908543
[patent_app_country] => US
[patent_app_date] => 2013-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6540
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13908543
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/908543 | Semiconductor device and operating method thereof | Jun 2, 2013 | Issued |
Array
(
[id] => 10860808
[patent_doc_number] => 08887027
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-11
[patent_title] => 'Solid-state mass storage device and method for failure anticipation'
[patent_app_type] => utility
[patent_app_number] => 13/901827
[patent_app_country] => US
[patent_app_date] => 2013-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5267
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13901827
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/901827 | Solid-state mass storage device and method for failure anticipation | May 23, 2013 | Issued |
Array
(
[id] => 9044082
[patent_doc_number] => 20130246720
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-19
[patent_title] => 'Providing Reliability Metrics For Decoding Data In Non-Volatile Storage'
[patent_app_type] => utility
[patent_app_number] => 13/888145
[patent_app_country] => US
[patent_app_date] => 2013-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 21696
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13888145
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/888145 | Providing reliability metrics for decoding data in non-volatile storage | May 5, 2013 | Issued |
Array
(
[id] => 10179613
[patent_doc_number] => 09209837
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-12-08
[patent_title] => 'Methods, algorithms, software, circuits, receivers and systems for decoding convolutional code'
[patent_app_type] => utility
[patent_app_number] => 13/871520
[patent_app_country] => US
[patent_app_date] => 2013-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 11200
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13871520
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/871520 | Methods, algorithms, software, circuits, receivers and systems for decoding convolutional code | Apr 25, 2013 | Issued |
Array
(
[id] => 10885621
[patent_doc_number] => 08910024
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-12-09
[patent_title] => 'Systems and methods for encoding data to meet an output constraint'
[patent_app_type] => utility
[patent_app_number] => 13/855879
[patent_app_country] => US
[patent_app_date] => 2013-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7536
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13855879
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/855879 | Systems and methods for encoding data to meet an output constraint | Apr 2, 2013 | Issued |