
Calvin E. Vansant
Examiner (ID: 11143, Phone: (571)272-5714 , Office: P/2915 )
| Most Active Art Unit | 2915 |
| Art Unit(s) | 2937, 2961, 2915 |
| Total Applications | 1582 |
| Issued Applications | 1536 |
| Pending Applications | 8 |
| Abandoned Applications | 37 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8176774
[patent_doc_number] => 20120110415
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-03
[patent_title] => 'DECODING APPARATUS, METHOD, AND PROGRAM'
[patent_app_type] => utility
[patent_app_number] => 13/238397
[patent_app_country] => US
[patent_app_date] => 2011-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6455
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20120110415.pdf
[firstpage_image] =>[orig_patent_app_number] => 13238397
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/238397 | DECODING APPARATUS, METHOD, AND PROGRAM | Sep 20, 2011 | Abandoned |
Array
(
[id] => 8497866
[patent_doc_number] => 20120297273
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-22
[patent_title] => 'MEMORY CONTROLLER, SEMICONDUCTOR MEMORY APPARATUS AND DECODING METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/235395
[patent_app_country] => US
[patent_app_date] => 2011-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8470
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13235395
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/235395 | Memory controller, semiconductor memory apparatus and decoding method | Sep 17, 2011 | Issued |
Array
(
[id] => 8046153
[patent_doc_number] => 20120072809
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-22
[patent_title] => 'DECODER, METHOD OF OPERATING THE SAME, AND APPARATUSES INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/234130
[patent_app_country] => US
[patent_app_date] => 2011-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 7217
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0072/20120072809.pdf
[firstpage_image] =>[orig_patent_app_number] => 13234130
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/234130 | Decoder, method of operating the same, and apparatuses including the same | Sep 14, 2011 | Issued |
Array
(
[id] => 10065723
[patent_doc_number] => 09104571
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-11
[patent_title] => 'Monitoring device of integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 13/232241
[patent_app_country] => US
[patent_app_date] => 2011-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4700
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13232241
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/232241 | Monitoring device of integrated circuit | Sep 13, 2011 | Issued |
Array
(
[id] => 10847799
[patent_doc_number] => 08875001
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-10-28
[patent_title] => 'Circuitry for parallel decoding of data blocks'
[patent_app_type] => utility
[patent_app_number] => 13/228406
[patent_app_country] => US
[patent_app_date] => 2011-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 6791
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228406
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/228406 | Circuitry for parallel decoding of data blocks | Sep 7, 2011 | Issued |
Array
(
[id] => 8632939
[patent_doc_number] => 08365038
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-01-29
[patent_title] => 'Method of determining a coordinate value with respect to patterns printed on a document'
[patent_app_type] => utility
[patent_app_number] => 13/224329
[patent_app_country] => US
[patent_app_date] => 2011-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 10805
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224329
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/224329 | Method of determining a coordinate value with respect to patterns printed on a document | Sep 1, 2011 | Issued |
Array
(
[id] => 10885142
[patent_doc_number] => 08909544
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-09
[patent_title] => 'Method for encoding or decoding digital data, data disseminating device and data managing device'
[patent_app_type] => utility
[patent_app_number] => 13/210257
[patent_app_country] => US
[patent_app_date] => 2011-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3300
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13210257
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/210257 | Method for encoding or decoding digital data, data disseminating device and data managing device | Aug 14, 2011 | Issued |
Array
(
[id] => 9458622
[patent_doc_number] => 08719648
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-06
[patent_title] => 'Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture'
[patent_app_type] => utility
[patent_app_number] => 13/192051
[patent_app_country] => US
[patent_app_date] => 2011-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8132
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13192051
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/192051 | Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture | Jul 26, 2011 | Issued |
Array
(
[id] => 8893812
[patent_doc_number] => 20130166996
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-27
[patent_title] => 'Communication Method and Echo'
[patent_app_type] => utility
[patent_app_number] => 13/816068
[patent_app_country] => US
[patent_app_date] => 2011-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1261
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13816068
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/816068 | Communication Method and Echo | Jul 21, 2011 | Abandoned |
Array
(
[id] => 8823880
[patent_doc_number] => 20130124925
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-16
[patent_title] => 'METHOD AND APPARATUS FOR CHECKING A MAIN MEMORY OF A PROCESSOR'
[patent_app_type] => utility
[patent_app_number] => 13/810491
[patent_app_country] => US
[patent_app_date] => 2011-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3416
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13810491
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/810491 | METHOD AND APPARATUS FOR CHECKING A MAIN MEMORY OF A PROCESSOR | Jun 30, 2011 | Abandoned |
Array
(
[id] => 8033775
[patent_doc_number] => 08145981
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-27
[patent_title] => 'Soft bit data transmission for error correction control in non-volatile memory'
[patent_app_type] => utility
[patent_app_number] => 13/164401
[patent_app_country] => US
[patent_app_date] => 2011-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 20
[patent_no_of_words] => 14241
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/145/08145981.pdf
[firstpage_image] =>[orig_patent_app_number] => 13164401
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/164401 | Soft bit data transmission for error correction control in non-volatile memory | Jun 19, 2011 | Issued |
Array
(
[id] => 10873311
[patent_doc_number] => 08898532
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-25
[patent_title] => 'Multi-carier configuration, activation and scheduling'
[patent_app_type] => utility
[patent_app_number] => 13/110858
[patent_app_country] => US
[patent_app_date] => 2011-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3001
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13110858
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/110858 | Multi-carier configuration, activation and scheduling | May 17, 2011 | Issued |
Array
(
[id] => 8235612
[patent_doc_number] => 08201060
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-06-12
[patent_title] => 'Methods and systems for rapid error correction of Reed-Solomon codes'
[patent_app_type] => utility
[patent_app_number] => 13/103309
[patent_app_country] => US
[patent_app_date] => 2011-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 24
[patent_no_of_words] => 22638
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/201/08201060.pdf
[firstpage_image] =>[orig_patent_app_number] => 13103309
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/103309 | Methods and systems for rapid error correction of Reed-Solomon codes | May 8, 2011 | Issued |
Array
(
[id] => 6052386
[patent_doc_number] => 20110209033
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-25
[patent_title] => 'CIRCUIT AND TECHNIQUE FOR REDUCING PARITY BIT-WIDTHS FOR CHECK BIT AND SYNDROME GENERATION FOR DATA BLOCKS THROUGH THE USE OF ADDITIONAL CHECK BITS TO INCREASE THE NUMBER OF MINIMUM WEIGHTED CODES IN THE HAMMING CODE H-MATRIX'
[patent_app_type] => utility
[patent_app_number] => 13/102522
[patent_app_country] => US
[patent_app_date] => 2011-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3289
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0209/20110209033.pdf
[firstpage_image] =>[orig_patent_app_number] => 13102522
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/102522 | Circuit and technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix | May 5, 2011 | Issued |
Array
(
[id] => 5960874
[patent_doc_number] => 20110185261
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-07-28
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/080035
[patent_app_country] => US
[patent_app_date] => 2011-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
[patent_figures_cnt] => 47
[patent_no_of_words] => 14413
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20110185261.pdf
[firstpage_image] =>[orig_patent_app_number] => 13080035
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/080035 | Semiconductor memory device | Apr 4, 2011 | Issued |
Array
(
[id] => 6191232
[patent_doc_number] => 20110173516
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-07-14
[patent_title] => 'METHOD AND DEVICE FOR INFORMATION BLOCK CODING AND SYNCHRONIZATION DETECTING'
[patent_app_type] => utility
[patent_app_number] => 13/075931
[patent_app_country] => US
[patent_app_date] => 2011-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8458
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0173/20110173516.pdf
[firstpage_image] =>[orig_patent_app_number] => 13075931
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/075931 | Method and device for information block coding and synchronization detecting | Mar 29, 2011 | Issued |
Array
(
[id] => 8208272
[patent_doc_number] => 08190984
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-29
[patent_title] => 'Memory and method for checking reading errors thereof'
[patent_app_type] => utility
[patent_app_number] => 13/070008
[patent_app_country] => US
[patent_app_date] => 2011-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3090
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/190/08190984.pdf
[firstpage_image] =>[orig_patent_app_number] => 13070008
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/070008 | Memory and method for checking reading errors thereof | Mar 22, 2011 | Issued |
Array
(
[id] => 9229717
[patent_doc_number] => 08635397
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-21
[patent_title] => 'Data writing method and system'
[patent_app_type] => utility
[patent_app_number] => 13/070186
[patent_app_country] => US
[patent_app_date] => 2011-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4646
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13070186
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/070186 | Data writing method and system | Mar 22, 2011 | Issued |
Array
(
[id] => 8419047
[patent_doc_number] => 20120246547
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-09-27
[patent_title] => 'HIGH RATE LOCALLY DECODABLE CODES'
[patent_app_type] => utility
[patent_app_number] => 13/052136
[patent_app_country] => US
[patent_app_date] => 2011-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4741
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13052136
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/052136 | High rate locally decodable codes | Mar 20, 2011 | Issued |
Array
(
[id] => 8303194
[patent_doc_number] => 20120185753
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-19
[patent_title] => 'Structure of ECC Spare Bits in 3D Memory'
[patent_app_type] => utility
[patent_app_number] => 13/052762
[patent_app_country] => US
[patent_app_date] => 2011-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4877
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13052762
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/052762 | Structure of ECC spare bits in 3D memory | Mar 20, 2011 | Issued |