Search

Calvin Lee

Examiner (ID: 8645, Phone: (571)272-1896 , Office: P/2896 )

Most Active Art Unit
2896
Art Unit(s)
2892, 2818, 2896, 2815, 2825
Total Applications
2071
Issued Applications
1934
Pending Applications
11
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12202662 [patent_doc_number] => 09905735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-27 [patent_title] => 'High brightness, low-cri semiconductor light emitting devices including narrow-spectrum luminescent materials' [patent_app_type] => utility [patent_app_number] => 15/475366 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 16577 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475366 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475366
High brightness, low-cri semiconductor light emitting devices including narrow-spectrum luminescent materials Mar 30, 2017 Issued
Array ( [id] => 11732905 [patent_doc_number] => 20170194347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'VERTICAL SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/464983 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13208 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15464983 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/464983
Vertical semiconductor device Mar 20, 2017 Issued
Array ( [id] => 11718246 [patent_doc_number] => 20170186744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING CONTACT PLUG AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/460897 [patent_app_country] => US [patent_app_date] => 2017-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 13138 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15460897 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/460897
Semiconductor device having contact plug and method of forming the same Mar 15, 2017 Issued
Array ( [id] => 11718210 [patent_doc_number] => 20170186709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'MANUFACTURING METHOD OF CHIP PACKAGE AND PACKAGE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/455200 [patent_app_country] => US [patent_app_date] => 2017-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15455200 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/455200
Manufacturing method of chip package and package substrate Mar 9, 2017 Issued
Array ( [id] => 11952387 [patent_doc_number] => 20170256538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'HYBRID STRUCTURE WITH SEPARATE CONTROLS' [patent_app_type] => utility [patent_app_number] => 15/449391 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8965 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449391 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/449391
Hybrid structure with separate controls Mar 2, 2017 Issued
Array ( [id] => 11710608 [patent_doc_number] => 20170179107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED BREAKDOWN VOLTAGE' [patent_app_type] => utility [patent_app_number] => 15/445640 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7778 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15445640 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/445640
Transient voltage suppressor (TVS) with reduced breakdown voltage Feb 27, 2017 Issued
Array ( [id] => 13378711 [patent_doc_number] => 20180240897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => HETEROJUNCTION BIPOLAR TRANSISTOR WITH A THICKENED EXTRINSIC BASE [patent_app_type] => utility [patent_app_number] => 15/437168 [patent_app_country] => US [patent_app_date] => 2017-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437168 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/437168
Heterojunction bipolar transistor with a thickened extrinsic base Feb 19, 2017 Issued
Array ( [id] => 15250633 [patent_doc_number] => 10510846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Semiconductor device with needle-shaped field plate structures in a transistor cell region and in an inner termination region [patent_app_type] => utility [patent_app_number] => 15/437191 [patent_app_country] => US [patent_app_date] => 2017-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 8288 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/437191
Semiconductor device with needle-shaped field plate structures in a transistor cell region and in an inner termination region Feb 19, 2017 Issued
Array ( [id] => 11623366 [patent_doc_number] => 20170133555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'METHOD FOR SEPARATING REGIONS OF A SEMICONDUCTOR LAYER' [patent_app_type] => utility [patent_app_number] => 15/413281 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3262 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15413281 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/413281
Method for separating regions of a semiconductor layer Jan 22, 2017 Issued
Array ( [id] => 11608668 [patent_doc_number] => 20170125973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'DUAL BOND PAD STRUCTURE FOR PHOTONICS' [patent_app_type] => utility [patent_app_number] => 15/407498 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2959 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15407498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/407498
Dual bond pad structure for photonics Jan 16, 2017 Issued
Array ( [id] => 12195556 [patent_doc_number] => 09899293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Semiconductor device packages with improved thermal management and related methods' [patent_app_type] => utility [patent_app_number] => 15/401762 [patent_app_country] => US [patent_app_date] => 2017-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15401762 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/401762
Semiconductor device packages with improved thermal management and related methods Jan 8, 2017 Issued
Array ( [id] => 11592782 [patent_doc_number] => 20170117194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'ASPECT RATIO FOR SEMICONDUCTOR ON INSULATOR' [patent_app_type] => utility [patent_app_number] => 15/400408 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400408 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/400408
Aspect ratio for semiconductor on insulator Jan 5, 2017 Issued
Array ( [id] => 14676945 [patent_doc_number] => 20190237587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => THIN FILM TRANSISTOR, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/340422 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16340422 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/340422
THIN FILM TRANSISTOR, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR Dec 29, 2016 Abandoned
Array ( [id] => 13293319 [patent_doc_number] => 10157860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Component stiffener architectures for microelectronic package structures [patent_app_type] => utility [patent_app_number] => 15/392145 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6071 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15392145 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/392145
Component stiffener architectures for microelectronic package structures Dec 27, 2016 Issued
Array ( [id] => 14063919 [patent_doc_number] => 10236262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => System and method for protecting an integrated circuit (IC) device [patent_app_type] => utility [patent_app_number] => 15/391924 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 6030 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391924 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/391924
System and method for protecting an integrated circuit (IC) device Dec 27, 2016 Issued
Array ( [id] => 11732856 [patent_doc_number] => 20170194299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'PACKAGE-ON-PACKAGE TYPE SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/392275 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6017 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15392275 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/392275
Package-on-package type semiconductor package and method of fabricating the same Dec 27, 2016 Issued
Array ( [id] => 12872677 [patent_doc_number] => 20180182734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => METHODS OF FORMING PACKAGE STRUCTURES FOR ENHANCED MEMORY CAPACITY AND STRUCTURES FORMED THEREBY [patent_app_type] => utility [patent_app_number] => 15/392006 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15392006 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/392006
Methods of forming package structures for enhanced memory capacity and structures formed thereby Dec 27, 2016 Issued
Array ( [id] => 12498948 [patent_doc_number] => 09997611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Graphene wiring structure and method for manufacturing graphene wiring structure [patent_app_type] => utility [patent_app_number] => 15/390899 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 7418 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390899 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/390899
Graphene wiring structure and method for manufacturing graphene wiring structure Dec 26, 2016 Issued
Array ( [id] => 12534936 [patent_doc_number] => 10008503 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-26 [patent_title] => Memory devices which include memory arrays [patent_app_type] => utility [patent_app_number] => 15/390959 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 6085 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390959 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/390959
Memory devices which include memory arrays Dec 26, 2016 Issued
Array ( [id] => 12990160 [patent_doc_number] => 20170345796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => ELECTRONIC DEVICE WITH STACKED ELECTRONIC CHIPS [patent_app_type] => utility [patent_app_number] => 15/391211 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391211 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/391211
ELECTRONIC DEVICE WITH STACKED ELECTRONIC CHIPS Dec 26, 2016 Abandoned
Menu