
Calvin Lee
Examiner (ID: 8645, Phone: (571)272-1896 , Office: P/2896 )
| Most Active Art Unit | 2896 |
| Art Unit(s) | 2892, 2818, 2896, 2815, 2825 |
| Total Applications | 2071 |
| Issued Applications | 1934 |
| Pending Applications | 11 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5549831
[patent_doc_number] => 20090283817
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[patent_kind] => A1
[patent_issue_date] => 2009-11-19
[patent_title] => 'FLOATING GATE STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 12/165272
[patent_app_country] => US
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Array
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[patent_title] => 'INSULATOR MATERIAL OVER BURIED CONDUCTIVE LINE'
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Array
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[patent_issue_date] => 2009-01-15
[patent_title] => 'DIRECT BOND SUBSTRATE OF IMPROVED BONDED INTERFACE HEAT RESISTANCE'
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Array
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[patent_title] => 'Method of manufacturing semiconductor device'
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Array
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Array
(
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[patent_title] => 'Inverter with Four-Transistor Schmitt Trigger'
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Array
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Array
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[patent_title] => 'METHOD FOR ETCHING A SUBSTRATE AND A DEVICE FORMED USING THE METHOD'
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[patent_app_number] => 12/137692
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/137692 | METHOD FOR ETCHING A SUBSTRATE AND A DEVICE FORMED USING THE METHOD | Jun 11, 2008 | Abandoned |
Array
(
[id] => 5364882
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/133892 | COL (Chip-On-Lead) multi-chip package | Jun 4, 2008 | Issued |
Array
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[patent_issue_date] => 2009-05-26
[patent_title] => 'Multi-chip semiconductor device with high withstand voltage, and a fabrication method of the same'
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Array
(
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[patent_title] => 'METHOD FOR MANUFACTURING SEMICONDCUTOR SENSOR'
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Array
(
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Array
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[id] => 102371
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Array
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Array
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Array
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Array
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