Search

Calvin Lee

Examiner (ID: 8645, Phone: (571)272-1896 , Office: P/2896 )

Most Active Art Unit
2896
Art Unit(s)
2892, 2818, 2896, 2815, 2825
Total Applications
2071
Issued Applications
1934
Pending Applications
11
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5549831 [patent_doc_number] => 20090283817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'FLOATING GATE STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/165272 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5923 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20090283817.pdf [firstpage_image] =>[orig_patent_app_number] => 12165272 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165272
Floating gate structures Jun 29, 2008 Issued
Array ( [id] => 5461605 [patent_doc_number] => 20090321805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'INSULATOR MATERIAL OVER BURIED CONDUCTIVE LINE' [patent_app_type] => utility [patent_app_number] => 12/165072 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 3139 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20090321805.pdf [firstpage_image] =>[orig_patent_app_number] => 12165072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165072
INSULATOR MATERIAL OVER BURIED CONDUCTIVE LINE Jun 29, 2008 Abandoned
Array ( [id] => 5307474 [patent_doc_number] => 20090014755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'DIRECT BOND SUBSTRATE OF IMPROVED BONDED INTERFACE HEAT RESISTANCE' [patent_app_type] => utility [patent_app_number] => 12/146672 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20090014755.pdf [firstpage_image] =>[orig_patent_app_number] => 12146672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146672
DIRECT BOND SUBSTRATE OF IMPROVED BONDED INTERFACE HEAT RESISTANCE Jun 25, 2008 Abandoned
Array ( [id] => 102422 [patent_doc_number] => 07723177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/142872 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3032 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/723/07723177.pdf [firstpage_image] =>[orig_patent_app_number] => 12142872 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/142872
Method of manufacturing semiconductor device Jun 19, 2008 Issued
Array ( [id] => 63639 [patent_doc_number] => 07759176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Thin film transistor array panel and methods for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/143685 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 46 [patent_no_of_words] => 8696 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/759/07759176.pdf [firstpage_image] =>[orig_patent_app_number] => 12143685 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/143685
Thin film transistor array panel and methods for manufacturing the same Jun 19, 2008 Issued
Array ( [id] => 4958392 [patent_doc_number] => 20080272816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Inverter with Four-Transistor Schmitt Trigger' [patent_app_type] => utility [patent_app_number] => 12/142602 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5072 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20080272816.pdf [firstpage_image] =>[orig_patent_app_number] => 12142602 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/142602
Inverter with four-transistor Schmitt trigger Jun 18, 2008 Issued
Array ( [id] => 4719477 [patent_doc_number] => 20080242000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'WAFER-LEVEL-CHIP-SCALE PACKAGE AND METHOD OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 12/139771 [patent_app_country] => US [patent_app_date] => 2008-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2704 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20080242000.pdf [firstpage_image] =>[orig_patent_app_number] => 12139771 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/139771
Wafer-level-chip-scale package and method of fabrication Jun 15, 2008 Issued
Array ( [id] => 4947015 [patent_doc_number] => 20080303141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'METHOD FOR ETCHING A SUBSTRATE AND A DEVICE FORMED USING THE METHOD' [patent_app_type] => utility [patent_app_number] => 12/137692 [patent_app_country] => US [patent_app_date] => 2008-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3406 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20080303141.pdf [firstpage_image] =>[orig_patent_app_number] => 12137692 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/137692
METHOD FOR ETCHING A SUBSTRATE AND A DEVICE FORMED USING THE METHOD Jun 11, 2008 Abandoned
Array ( [id] => 5364882 [patent_doc_number] => 20090302441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'COL (CHIP-ON-LEAD) MULTI-CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/133892 [patent_app_country] => US [patent_app_date] => 2008-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4204 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20090302441.pdf [firstpage_image] =>[orig_patent_app_number] => 12133892 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/133892
COL (Chip-On-Lead) multi-chip package Jun 4, 2008 Issued
Array ( [id] => 300235 [patent_doc_number] => 07538439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Multi-chip semiconductor device with high withstand voltage, and a fabrication method of the same' [patent_app_type] => utility [patent_app_number] => 12/133715 [patent_app_country] => US [patent_app_date] => 2008-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2807 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538439.pdf [firstpage_image] =>[orig_patent_app_number] => 12133715 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/133715
Multi-chip semiconductor device with high withstand voltage, and a fabrication method of the same Jun 4, 2008 Issued
Array ( [id] => 4719461 [patent_doc_number] => 20080241984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDCUTOR SENSOR' [patent_app_type] => utility [patent_app_number] => 12/133791 [patent_app_country] => US [patent_app_date] => 2008-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11044 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20080241984.pdf [firstpage_image] =>[orig_patent_app_number] => 12133791 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/133791
Method for manufacturing semiconductor sensor Jun 4, 2008 Issued
Array ( [id] => 5300192 [patent_doc_number] => 20090294844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/132181 [patent_app_country] => US [patent_app_date] => 2008-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 8388 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20090294844.pdf [firstpage_image] =>[orig_patent_app_number] => 12132181 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/132181
Semiconductor device Jun 2, 2008 Issued
Array ( [id] => 102371 [patent_doc_number] => 07723142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Growth method of GaN crystal, and GaN crystal substrate' [patent_app_type] => utility [patent_app_number] => 12/130082 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 18714 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/723/07723142.pdf [firstpage_image] =>[orig_patent_app_number] => 12130082 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/130082
Growth method of GaN crystal, and GaN crystal substrate May 29, 2008 Issued
Array ( [id] => 204496 [patent_doc_number] => 07629215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/128682 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 9188 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/629/07629215.pdf [firstpage_image] =>[orig_patent_app_number] => 12128682 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128682
Semiconductor device and method of manufacturing the same May 28, 2008 Issued
Array ( [id] => 5300271 [patent_doc_number] => 20090294923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Structure and Method for Reducing Threshold Voltage Variation' [patent_app_type] => utility [patent_app_number] => 12/128772 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1686 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20090294923.pdf [firstpage_image] =>[orig_patent_app_number] => 12128772 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128772
Structure and method for reducing threshold voltage variation May 28, 2008 Issued
Array ( [id] => 185020 [patent_doc_number] => 07648911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias' [patent_app_type] => utility [patent_app_number] => 12/127472 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 5998 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/648/07648911.pdf [firstpage_image] =>[orig_patent_app_number] => 12127472 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127472
Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias May 26, 2008 Issued
Array ( [id] => 4837472 [patent_doc_number] => 20080278071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'ORGANIC LIGHT-EMITTING DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/126263 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3182 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20080278071.pdf [firstpage_image] =>[orig_patent_app_number] => 12126263 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/126263
Organic light-emitting device and method of fabricating the same May 22, 2008 Issued
Array ( [id] => 4552523 [patent_doc_number] => 07960742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Active device array substrate having organic material layer with concave patterns' [patent_app_type] => utility [patent_app_number] => 12/123481 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3866 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/960/07960742.pdf [firstpage_image] =>[orig_patent_app_number] => 12123481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/123481
Active device array substrate having organic material layer with concave patterns May 19, 2008 Issued
Array ( [id] => 4775834 [patent_doc_number] => 20080283832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Integrated Circuit Comprising an Amorphous Region and Method of Manufacturing an Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 12/122892 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3159 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20080283832.pdf [firstpage_image] =>[orig_patent_app_number] => 12122892 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/122892
Integrated circuit comprising an amorphous region and method of manufacturing an integrated circuit May 18, 2008 Issued
Array ( [id] => 224827 [patent_doc_number] => 07605010 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-20 [patent_title] => 'Integrated silicon optical isolator' [patent_app_type] => utility [patent_app_number] => 12/122771 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3556 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/605/07605010.pdf [firstpage_image] =>[orig_patent_app_number] => 12122771 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/122771
Integrated silicon optical isolator May 18, 2008 Issued
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