Search

Calvin Y Choi

Examiner (ID: 9451, Phone: (571)270-7882 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812, 4116
Total Applications
1008
Issued Applications
793
Pending Applications
53
Abandoned Applications
162

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14033349 [patent_doc_number] => 10228420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit [patent_app_type] => utility [patent_app_number] => 15/268848 [patent_app_country] => US [patent_app_date] => 2016-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4439 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15268848 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/268848
Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit Sep 18, 2016 Issued
Array ( [id] => 14147937 [patent_doc_number] => 10254340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Independently driving built-in self test circuitry over a range of operating conditions [patent_app_type] => utility [patent_app_number] => 15/267319 [patent_app_country] => US [patent_app_date] => 2016-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7386 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267319 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/267319
Independently driving built-in self test circuitry over a range of operating conditions Sep 15, 2016 Issued
Array ( [id] => 12242028 [patent_doc_number] => 20180074891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'Storage System and Method for Reducing XOR Recovery Time' [patent_app_type] => utility [patent_app_number] => 15/264279 [patent_app_country] => US [patent_app_date] => 2016-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15264279 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/264279
Storage system and method for reducing XOR recovery time by excluding invalid data from XOR parity Sep 12, 2016 Issued
Array ( [id] => 11340189 [patent_doc_number] => 20160365946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'Transmitter and transmission method for broadcasting data in a broadcasting system\nproviding incremental redundancy' [patent_app_type] => utility [patent_app_number] => 15/250489 [patent_app_country] => US [patent_app_date] => 2016-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13980 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15250489 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/250489
Transmitter and receiver for transmitting basic codeword portion and auxiliary codeword portion of a codeword in different frames Aug 28, 2016 Issued
Array ( [id] => 11938636 [patent_doc_number] => 20170242786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'MEMORY SYSTEM AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/234942 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12876 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234942 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/234942
MEMORY SYSTEM AND OPERATION METHOD THEREOF Aug 10, 2016 Abandoned
Array ( [id] => 12187467 [patent_doc_number] => 20180046403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'HYBRID AND ADAPTIVE DISPERSED STORAGE NETWORK (DSN) MEMORY' [patent_app_type] => utility [patent_app_number] => 15/233712 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9150 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233712 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/233712
Expanding a dispersed storage network (DSN) Aug 9, 2016 Issued
Array ( [id] => 12187607 [patent_doc_number] => 20180046543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'ERASURE CODES TO PREVENT LOWER PAGE CORRUPTION IN FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 15/232058 [patent_app_country] => US [patent_app_date] => 2016-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15232058 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/232058
Erasure codes to prevent lower page corruption in flash memory Aug 8, 2016 Issued
Array ( [id] => 12180637 [patent_doc_number] => 20180039573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'Apparatus and Method of Wear Leveling for Storage Class Memory' [patent_app_type] => utility [patent_app_number] => 15/230414 [patent_app_country] => US [patent_app_date] => 2016-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8768 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15230414 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/230414
Apparatus and method of wear leveling for storage class memory using cache filtering Aug 5, 2016 Issued
Array ( [id] => 12180600 [patent_doc_number] => 20180039537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'SYSTEMS AND METHODS FOR CORRECTING DATA ERRORS IN MEMORY' [patent_app_type] => utility [patent_app_number] => 15/228294 [patent_app_country] => US [patent_app_date] => 2016-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7543 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15228294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/228294
Systems and methods for correcting data errors in memory susceptible to data loss when subjected to elevated temperatures Aug 3, 2016 Issued
Array ( [id] => 11118660 [patent_doc_number] => 20160315635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'ERROR CORRECTION CODE (ECC) SELECTION USING PROBABILITY DENSITY FUNCTIONS OF ERROR CORRECTION CAPABILITY IN STORAGE CONTROLLERS WITH MULTIPLE ERROR CORRECTION CODES' [patent_app_type] => utility [patent_app_number] => 15/198533 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7786 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198533 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/198533
Error correction code (ECC) selection using probability density functions of error correction capability in storage controllers with multiple error correction codes Jun 29, 2016 Issued
Array ( [id] => 11095105 [patent_doc_number] => 20160292073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'TIME DE-INTERLEAVING CIRCUIT AND TIME DE-INTERLEAVING METHOD' [patent_app_type] => utility [patent_app_number] => 15/083499 [patent_app_country] => US [patent_app_date] => 2016-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9509 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15083499 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/083499
Time de-interleaving circuit and time de-interleaving method for reducing a number of times of accessing memory Mar 28, 2016 Issued
Array ( [id] => 13029251 [patent_doc_number] => 10037245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Raid system performance enhancement using compressed data and byte addressable storage devices [patent_app_type] => utility [patent_app_number] => 15/083327 [patent_app_country] => US [patent_app_date] => 2016-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15083327 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/083327
Raid system performance enhancement using compressed data and byte addressable storage devices Mar 28, 2016 Issued
Array ( [id] => 11965686 [patent_doc_number] => 20170269839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'ERROR CORRECTION CODE PROCESSING AND DATA SHAPING' [patent_app_type] => utility [patent_app_number] => 15/073373 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 24957 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073373 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073373
Error correction code processing and data shaping for reducing wear to a memory Mar 16, 2016 Issued
Array ( [id] => 12551241 [patent_doc_number] => 10013296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Method of fault tolerance in combinational circuits [patent_app_type] => utility [patent_app_number] => 15/015654 [patent_app_country] => US [patent_app_date] => 2016-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 14697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15015654 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/015654
Method of fault tolerance in combinational circuits Feb 3, 2016 Issued
Array ( [id] => 11840937 [patent_doc_number] => 20170222659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'POWER IMPROVEMENT FOR LDPC' [patent_app_type] => utility [patent_app_number] => 15/012872 [patent_app_country] => US [patent_app_date] => 2016-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2113 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15012872 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/012872
POWER IMPROVEMENT FOR LDPC Feb 1, 2016 Abandoned
Array ( [id] => 11838696 [patent_doc_number] => 20170220416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'Segmented Error Coding for Block-Based Memory' [patent_app_type] => utility [patent_app_number] => 15/011785 [patent_app_country] => US [patent_app_date] => 2016-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15011785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/011785
Segmented error coding for block-based memory Jan 31, 2016 Issued
Array ( [id] => 13641773 [patent_doc_number] => 09847853 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-19 [patent_title] => Method and apparatus for reduced HARQ buffer storage [patent_app_type] => utility [patent_app_number] => 15/008779 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6350 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15008779 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/008779
Method and apparatus for reduced HARQ buffer storage Jan 27, 2016 Issued
Array ( [id] => 14334477 [patent_doc_number] => 10298271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Method and apparatus for providing a joint error correction code for a combined data frame comprising first data of a first data channel and second data of a second data channel and sensor system [patent_app_type] => utility [patent_app_number] => 15/003230 [patent_app_country] => US [patent_app_date] => 2016-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15003230 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/003230
Method and apparatus for providing a joint error correction code for a combined data frame comprising first data of a first data channel and second data of a second data channel and sensor system Jan 20, 2016 Issued
Array ( [id] => 10771064 [patent_doc_number] => 20160117220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'DATA STORAGE DEVICE AND ERROR CORRECTION METHOD CAPABLE OF ADJUSTING VOLTAGE DISTRIBUTION' [patent_app_type] => utility [patent_app_number] => 14/989080 [patent_app_country] => US [patent_app_date] => 2016-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5363 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14989080 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/989080
Data storage device and error correction method capable of adjusting voltage distribution by reading pages Jan 5, 2016 Issued
Array ( [id] => 11847363 [patent_doc_number] => 09734920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories' [patent_app_type] => utility [patent_app_number] => 14/867299 [patent_app_country] => US [patent_app_date] => 2015-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5418 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14867299 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/867299
Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories Sep 27, 2015 Issued
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