Calvin Y Choi

Array ( [id] => 10645126 [patent_doc_number] => 09361999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Data storage device and error correction method capable of adjusting voltage distribution' [patent_app_type] => utility [patent_app_number] => 14/271897 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5339 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11924590 [patent_doc_number] => 09792173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Interface control circuit, memory system, and method of controlling an interface control circuit' [patent_app_type] => utility [patent_app_number] => 14/271732 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 21267 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10934637 [patent_doc_number] => 20140337658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'FREQUENCY EXECUTION MONITORING' [patent_app_type] => utility [patent_app_number] => 14/272120 [patent_app_country] => US [patent_app_date] => 2014-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3183 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10439254 [patent_doc_number] => 20150324265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'TESTING I/O TIMING DEFECTS FOR HIGH PIN COUNT, NON-CONTACT INTERFACES' [patent_app_type] => utility [patent_app_number] => 14/270503 [patent_app_country] => US [patent_app_date] => 2014-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12054 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14270503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11232768 [patent_doc_number] => 09459997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Error injection and error counting during memory scrubbing operations' [patent_app_type] => utility [patent_app_number] => 14/266984 [patent_app_country] => US [patent_app_date] => 2014-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6652 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14266984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10401519 [patent_doc_number] => 20150286528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'ERROR CORRECTION CODE (ECC) SELECTION IN NAND FLASH CONTROLLERS WITH MULTIPLE ERROR CORRECTION CODES' [patent_app_type] => utility [patent_app_number] => 14/264419 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7773 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11193380 [patent_doc_number] => 09424195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Dynamic remapping of cache lines' [patent_app_type] => utility [patent_app_number] => 14/253785 [patent_app_country] => US [patent_app_date] => 2014-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7136 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14253785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11280411 [patent_doc_number] => 09496897 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-15 [patent_title] => 'Methods and apparatus for generating authenticated error correcting codes' [patent_app_type] => utility [patent_app_number] => 14/230655 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11914 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11570404 [patent_doc_number] => 20170109048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'MEMORY UNIT WITH DATA SEGMENT INFORMATION IN HEADER' [patent_app_type] => utility [patent_app_number] => 15/128476 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2390 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15128476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14037471 [patent_doc_number] => 10230501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Technique for storing softbits [patent_app_type] => utility [patent_app_number] => 15/117809 [patent_app_country] => US [patent_app_date] => 2014-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8425 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15117809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10395853 [patent_doc_number] => 20150280861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'CONTROL DEVICE AND METHOD FOR USE IN A BROADCAST SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/437417 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14437417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12173845 [patent_doc_number] => 09891989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Storage apparatus, storage system, and storage apparatus control method for updating stored data stored in nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 14/769205 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15025 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14769205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9214002 [patent_doc_number] => 20140013179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'TRANSMISSION DELAY DIFFERENCE CORRECTION METHOD, COMMUNICATION DEVICE, AND COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/026619 [patent_app_country] => US [patent_app_date] => 2013-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 23264 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14026619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9746075 [patent_doc_number] => 20140281794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'ERROR CORRECTION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/963125 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10435 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9398556 [patent_doc_number] => 20140095962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/963692 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9637175 [patent_doc_number] => 20140215284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'DYNAMIC SCALING PROCESSOR DEVICE AND PROCESSING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/960317 [patent_app_country] => US [patent_app_date] => 2013-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6564 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13960317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9308627 [patent_doc_number] => 20140047301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND A METHOD THEREIN' [patent_app_type] => utility [patent_app_number] => 13/957615 [patent_app_country] => US [patent_app_date] => 2013-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5308 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13957615 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9859958 [patent_doc_number] => 20150039976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'Efficient Error Correction of Multi-Bit Errors' [patent_app_type] => utility [patent_app_number] => 13/958047 [patent_app_country] => US [patent_app_date] => 2013-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18740 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13958047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9814590 [patent_doc_number] => 20150026536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'Data Decoder With Trapping Set Flip Bit Mapper' [patent_app_type] => utility [patent_app_number] => 13/958162 [patent_app_country] => US [patent_app_date] => 2013-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13958162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9688336 [patent_doc_number] => 20140245101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 13/956824 [patent_app_country] => US [patent_app_date] => 2013-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6469 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13956824 [rel_patent_id] =>[rel_patent_doc_number] =>)