Calvin Y Choi
Examiner (ID: 9451, Phone: (571)270-7882 , Office: P/2812 )
Most Active Art Unit | 2812 |
Art Unit(s) | 2812, 4116 |
Total Applications | 1008 |
Issued Applications | 793 |
Pending Applications | 53 |
Abandoned Applications | 162 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 11739042
[patent_doc_number] => 09703625
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-07-11
[patent_title] => 'Method and apparatus for detecting or correcting multi-bit errors in computer memory systems'
[patent_app_type] => utility
[patent_app_number] => 13/830195
[patent_app_country] => US
[patent_app_date] => 2013-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2589
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13830195
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/830195 | Method and apparatus for detecting or correcting multi-bit errors in computer memory systems | Mar 13, 2013 | Issued |
Array
(
[id] => 10098070
[patent_doc_number] => 09134377
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-15
[patent_title] => 'Method and apparatus for device testing using multiple processing paths'
[patent_app_type] => utility
[patent_app_number] => 13/826038
[patent_app_country] => US
[patent_app_date] => 2013-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 23
[patent_no_of_words] => 15366
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13826038
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/826038 | Method and apparatus for device testing using multiple processing paths | Mar 13, 2013 | Issued |
Array
(
[id] => 8831741
[patent_doc_number] => 20130132787
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-23
[patent_title] => 'LIGHTING CONTROL PROTOCOL'
[patent_app_type] => utility
[patent_app_number] => 13/744858
[patent_app_country] => US
[patent_app_date] => 2013-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6199
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13744858
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/744858 | LIGHTING CONTROL PROTOCOL | Jan 17, 2013 | Abandoned |
Array
(
[id] => 9604902
[patent_doc_number] => 20140201584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-17
[patent_title] => 'SCAN TEST CIRCUITRY COMPRISING AT LEAST ONE SCAN CHAIN AND ASSOCIATED RESET MULTIPLEXING CIRCUITRY'
[patent_app_type] => utility
[patent_app_number] => 13/743687
[patent_app_country] => US
[patent_app_date] => 2013-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7003
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13743687
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/743687 | SCAN TEST CIRCUITRY COMPRISING AT LEAST ONE SCAN CHAIN AND ASSOCIATED RESET MULTIPLEXING CIRCUITRY | Jan 16, 2013 | Abandoned |
Array
(
[id] => 9604924
[patent_doc_number] => 20140201606
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-17
[patent_title] => 'ERROR PROTECTION FOR A DATA BUS'
[patent_app_type] => utility
[patent_app_number] => 13/741599
[patent_app_country] => US
[patent_app_date] => 2013-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5010
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13741599
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/741599 | Error protection for a data bus | Jan 14, 2013 | Issued |
Array
(
[id] => 9604900
[patent_doc_number] => 20140201583
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-17
[patent_title] => 'System and Method For Non-Intrusive Random Failure Emulation Within an Integrated Circuit'
[patent_app_type] => utility
[patent_app_number] => 13/742161
[patent_app_country] => US
[patent_app_date] => 2013-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2326
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742161
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/742161 | System and Method For Non-Intrusive Random Failure Emulation Within an Integrated Circuit | Jan 14, 2013 | Abandoned |
Array
(
[id] => 10591259
[patent_doc_number] => 09312883
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-04-12
[patent_title] => 'Hierarchical cyclic redundancy check circuitry'
[patent_app_type] => utility
[patent_app_number] => 13/742192
[patent_app_country] => US
[patent_app_date] => 2013-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 6619
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742192
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/742192 | Hierarchical cyclic redundancy check circuitry | Jan 14, 2013 | Issued |
Array
(
[id] => 11550469
[patent_doc_number] => 09619317
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-04-11
[patent_title] => 'Decoder having early decoding termination detection'
[patent_app_type] => utility
[patent_app_number] => 13/742248
[patent_app_country] => US
[patent_app_date] => 2013-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7101
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742248
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/742248 | Decoder having early decoding termination detection | Jan 14, 2013 | Issued |
Array
(
[id] => 9604925
[patent_doc_number] => 20140201607
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-17
[patent_title] => 'One-time programmable integrated circuit security'
[patent_app_type] => utility
[patent_app_number] => 13/741248
[patent_app_country] => US
[patent_app_date] => 2013-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8637
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13741248
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/741248 | One-time programmable integrated circuit security | Jan 13, 2013 | Issued |
Array
(
[id] => 8929857
[patent_doc_number] => 20130185617
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-18
[patent_title] => 'WIRELESS BACKHAUL COMMUNICATION'
[patent_app_type] => utility
[patent_app_number] => 13/740729
[patent_app_country] => US
[patent_app_date] => 2013-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5731
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13740729
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/740729 | WIRELESS BACKHAUL COMMUNICATION | Jan 13, 2013 | Abandoned |
Array
(
[id] => 10914456
[patent_doc_number] => 20140317475
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-23
[patent_title] => 'Adaptive Forward Error Correction (FEC) System and Method'
[patent_app_type] => utility
[patent_app_number] => 14/370030
[patent_app_country] => US
[patent_app_date] => 2012-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6556
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14370030
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/370030 | Adaptive forward error correction (FEC) system and method | Dec 30, 2012 | Issued |
Array
(
[id] => 9548744
[patent_doc_number] => 20140173392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-19
[patent_title] => 'HARDWARE ENFORCED PROTECTION OF SOFTWARE DATA STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 13/719937
[patent_app_country] => US
[patent_app_date] => 2012-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5207
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719937
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/719937 | HARDWARE ENFORCED PROTECTION OF SOFTWARE DATA STRUCTURES | Dec 18, 2012 | Abandoned |
Array
(
[id] => 9746118
[patent_doc_number] => 20140281838
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'SENSOR AND SENSING METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/353395
[patent_app_country] => US
[patent_app_date] => 2012-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6549
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14353395
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/353395 | SENSOR AND SENSING METHOD | Dec 3, 2012 | Abandoned |
Array
(
[id] => 10195590
[patent_doc_number] => 09224503
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-12-29
[patent_title] => 'Memory test with in-line error correction code logic'
[patent_app_type] => utility
[patent_app_number] => 13/683154
[patent_app_country] => US
[patent_app_date] => 2012-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5418
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13683154
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/683154 | Memory test with in-line error correction code logic | Nov 20, 2012 | Issued |
Array
(
[id] => 9225055
[patent_doc_number] => 20140019831
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-16
[patent_title] => 'METHOD FOR TRANSMITTING DATA PACKETS AND CORRESPONDING SYSTEM WITH DATA SOURCE AND DATA SINK'
[patent_app_type] => utility
[patent_app_number] => 13/681951
[patent_app_country] => US
[patent_app_date] => 2012-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2617
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681951
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/681951 | METHOD FOR TRANSMITTING DATA PACKETS AND CORRESPONDING SYSTEM WITH DATA SOURCE AND DATA SINK | Nov 19, 2012 | Abandoned |
Array
(
[id] => 9283018
[patent_doc_number] => 20140032986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-30
[patent_title] => 'SYSTEM AND METHOD FOR PERFORMING SCAN TEST'
[patent_app_type] => utility
[patent_app_number] => 13/681406
[patent_app_country] => US
[patent_app_date] => 2012-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6303
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681406
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/681406 | System and method for performing scan test | Nov 18, 2012 | Issued |
Array
(
[id] => 9493225
[patent_doc_number] => 20140143630
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-22
[patent_title] => 'DYNAMIC READ SCHEME FOR HIGH RELIABILITY HIGH PERFORMANCE FLASH MEMORY'
[patent_app_type] => utility
[patent_app_number] => 13/679481
[patent_app_country] => US
[patent_app_date] => 2012-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 12751
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13679481
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/679481 | Dynamic read scheme for high reliability high performance flash memory | Nov 15, 2012 | Issued |
Array
(
[id] => 9961352
[patent_doc_number] => 09009577
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-04-14
[patent_title] => 'Circuitry and method for forward error correction'
[patent_app_type] => utility
[patent_app_number] => 13/676043
[patent_app_country] => US
[patent_app_date] => 2012-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6667
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13676043
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/676043 | Circuitry and method for forward error correction | Nov 12, 2012 | Issued |
Array
(
[id] => 13654905
[patent_doc_number] => 09853780
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-12-26
[patent_title] => Dynamic HARQ-id reservation
[patent_app_type] => utility
[patent_app_number] => 14/354051
[patent_app_country] => US
[patent_app_date] => 2012-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 6522
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 357
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14354051
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/354051 | Dynamic HARQ-id reservation | Oct 23, 2012 | Issued |
Array
(
[id] => 10538432
[patent_doc_number] => 09264073
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-16
[patent_title] => 'Freezing-based LDPC decoder and method'
[patent_app_type] => utility
[patent_app_number] => 13/595846
[patent_app_country] => US
[patent_app_date] => 2012-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5323
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13595846
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/595846 | Freezing-based LDPC decoder and method | Aug 26, 2012 | Issued |