Cam N Nguyen
Examiner (ID: 5643, Phone: (571)272-1357 , Office: P/1736 )
Most Active Art Unit | 1736 |
Art Unit(s) | 1736, 1793, 1754 |
Total Applications | 2328 |
Issued Applications | 1758 |
Pending Applications | 181 |
Abandoned Applications | 389 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 11424936
[patent_doc_number] => 20170033082
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-02
[patent_title] => 'FACE-TO-FACE SEMICONDUCTOR ASSEMBLY HAVING SEMICONDUCTOR DEVICE IN DIELECTRIC RECESS'
[patent_app_type] => utility
[patent_app_number] => 14/986547
[patent_app_country] => US
[patent_app_date] => 2015-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9826
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14986547
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/986547 | Face-to-face semiconductor assembly having semiconductor device in dielectric recess | Dec 30, 2015 | Issued |
Array
(
[id] => 10982805
[patent_doc_number] => 20160179748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'METHOD AND APPARATUS FOR ESTIMATING WAVEFORM ONSET TIME'
[patent_app_type] => utility
[patent_app_number] => 14/971923
[patent_app_country] => US
[patent_app_date] => 2015-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7555
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14971923
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/971923 | METHOD AND APPARATUS FOR ESTIMATING WAVEFORM ONSET TIME | Dec 15, 2015 | Abandoned |
Array
(
[id] => 11034410
[patent_doc_number] => 20160231366
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-08-11
[patent_title] => 'METHOD FOR MEASURING ELECTRIC POWER VALUE IN AN HVDC SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 14/970234
[patent_app_country] => US
[patent_app_date] => 2015-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 11619
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970234
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/970234 | Method for measuring electric power value in an hvdc system | Dec 14, 2015 | Issued |
Array
(
[id] => 10825197
[patent_doc_number] => 20160171364
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-16
[patent_title] => 'OPTIMISTIC DATA RETRIEVAL IN A PROCESS CONTROL ENVIRONMENT'
[patent_app_type] => utility
[patent_app_number] => 14/970076
[patent_app_country] => US
[patent_app_date] => 2015-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5752
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970076
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/970076 | OPTIMISTIC DATA RETRIEVAL IN A PROCESS CONTROL ENVIRONMENT | Dec 14, 2015 | Abandoned |
Array
(
[id] => 10828174
[patent_doc_number] => 20160174344
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-16
[patent_title] => 'SYSTEM AND METHOD FOR REDUCING PEAK AND OFF-PEAK ELECTRICITY DEMAND BY MONITORING, CONTROLLING AND METERING LIGHTING IN A FACILITY'
[patent_app_type] => utility
[patent_app_number] => 14/968627
[patent_app_country] => US
[patent_app_date] => 2015-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 9498
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968627
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/968627 | System and method for reducing peak and off-peak electricity demand by monitoring, controlling and metering lighting in a facility | Dec 13, 2015 | Issued |
Array
(
[id] => 16594095
[patent_doc_number] => 10903372
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-26
[patent_title] => Metal-oxide-polysilicon tunable resistor for flexible circuit design and method of fabricating same
[patent_app_type] => utility
[patent_app_number] => 15/770009
[patent_app_country] => US
[patent_app_date] => 2015-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 45
[patent_no_of_words] => 8148
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15770009
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/770009 | Metal-oxide-polysilicon tunable resistor for flexible circuit design and method of fabricating same | Dec 10, 2015 | Issued |
Array
(
[id] => 10819648
[patent_doc_number] => 20160165812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-16
[patent_title] => 'MONITORING AND CONTROL SYSTEM AND METHOD FOR PLANT FACTORY BASED ON TV WHITE SPACES'
[patent_app_type] => utility
[patent_app_number] => 14/964888
[patent_app_country] => US
[patent_app_date] => 2015-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7952
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14964888
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/964888 | Monitoring and control system and method for plant factory based on TV white spaces | Dec 9, 2015 | Issued |
Array
(
[id] => 10611103
[patent_doc_number] => 09331148
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-05-03
[patent_title] => 'FinFET device with channel strain'
[patent_app_type] => utility
[patent_app_number] => 14/962194
[patent_app_country] => US
[patent_app_date] => 2015-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 3438
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 18
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14962194
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/962194 | FinFET device with channel strain | Dec 7, 2015 | Issued |
Array
(
[id] => 10979172
[patent_doc_number] => 20160176116
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'APPARATUS AND METHOD FOR AUTHORING THREE-DIMENSIONAL OBJECT FOR THREE-DIMENSIONAL PRINTING'
[patent_app_type] => utility
[patent_app_number] => 14/962110
[patent_app_country] => US
[patent_app_date] => 2015-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4949
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14962110
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/962110 | APPARATUS AND METHOD FOR AUTHORING THREE-DIMENSIONAL OBJECT FOR THREE-DIMENSIONAL PRINTING | Dec 7, 2015 | Abandoned |
Array
(
[id] => 10740910
[patent_doc_number] => 20160087061
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-24
[patent_title] => 'SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/960293
[patent_app_country] => US
[patent_app_date] => 2015-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5886
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14960293
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/960293 | Silicon carbide semiconductor device and manufacturing method of silicon carbide semiconductor device | Dec 3, 2015 | Issued |
Array
(
[id] => 10809650
[patent_doc_number] => 20160155809
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-02
[patent_title] => 'SEMICONDUCTOR COMPONENT WITH FIELD ELECTRODE BETWEEN ADJACENT SEMICONDUCTOR FINS AND METHOD FOR PRODUCING SUCH A SEMICONDUCTOR COMPONENT'
[patent_app_type] => utility
[patent_app_number] => 14/953103
[patent_app_country] => US
[patent_app_date] => 2015-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6202
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14953103
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/953103 | Semiconductor component with field electrode between adjacent semiconductor fins and method for producing such a semiconductor component | Nov 26, 2015 | Issued |
Array
(
[id] => 11831761
[patent_doc_number] => 09728510
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-08
[patent_title] => 'Cavity package with composite substrate'
[patent_app_type] => utility
[patent_app_number] => 14/952562
[patent_app_country] => US
[patent_app_date] => 2015-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 19
[patent_no_of_words] => 8217
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14952562
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/952562 | Cavity package with composite substrate | Nov 24, 2015 | Issued |
Array
(
[id] => 11898279
[patent_doc_number] => 09768219
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-19
[patent_title] => 'Imaging device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 14/952543
[patent_app_country] => US
[patent_app_date] => 2015-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 53
[patent_no_of_words] => 8865
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14952543
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/952543 | Imaging device and method of manufacturing the same | Nov 24, 2015 | Issued |
Array
(
[id] => 11891091
[patent_doc_number] => 09761657
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-12
[patent_title] => 'Metal-oxide-semiconductor transistor and method of forming gate layout'
[patent_app_type] => utility
[patent_app_number] => 14/952877
[patent_app_country] => US
[patent_app_date] => 2015-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4999
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14952877
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/952877 | Metal-oxide-semiconductor transistor and method of forming gate layout | Nov 24, 2015 | Issued |
Array
(
[id] => 11651084
[patent_doc_number] => 20170146984
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-25
[patent_title] => 'AUTOMATED FASTENER INSERT INSTALLATION SYSTEM FOR COMPOSITE PANELS'
[patent_app_type] => utility
[patent_app_number] => 14/949278
[patent_app_country] => US
[patent_app_date] => 2015-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6911
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14949278
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/949278 | Automated fastener insert installation system for composite panels | Nov 22, 2015 | Issued |
Array
(
[id] => 10725714
[patent_doc_number] => 20160071862
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-10
[patent_title] => 'SEMICONDUCTOR DEVICE WITH A PILLAR-SHAPED SEMICONDUCTOR LAYER'
[patent_app_type] => utility
[patent_app_number] => 14/944616
[patent_app_country] => US
[patent_app_date] => 2015-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 8907
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14944616
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/944616 | Semiconductor device with a pillar-shaped semiconductor layer | Nov 17, 2015 | Issued |
Array
(
[id] => 14011515
[patent_doc_number] => 10224233
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-05
[patent_title] => High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N
[patent_app_type] => utility
[patent_app_number] => 15/526864
[patent_app_country] => US
[patent_app_date] => 2015-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 7246
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 405
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15526864
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/526864 | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N | Nov 15, 2015 | Issued |
Array
(
[id] => 10718124
[patent_doc_number] => 20160064270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-03
[patent_title] => 'METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING AIR GAP SPACERS'
[patent_app_type] => utility
[patent_app_number] => 14/939439
[patent_app_country] => US
[patent_app_date] => 2015-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 81
[patent_figures_cnt] => 81
[patent_no_of_words] => 17421
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14939439
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/939439 | Methods of manufacturing semiconductor devices including air gap spacers | Nov 11, 2015 | Issued |
Array
(
[id] => 11831891
[patent_doc_number] => 09728642
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-08
[patent_title] => 'Retaining strain in finFET devices'
[patent_app_type] => utility
[patent_app_number] => 14/932112
[patent_app_country] => US
[patent_app_date] => 2015-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 4314
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14932112
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/932112 | Retaining strain in finFET devices | Nov 3, 2015 | Issued |
Array
(
[id] => 11293738
[patent_doc_number] => 20160343670
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-24
[patent_title] => 'FLEXIBLE DEVICE HAVING FLEXIBLE INTERCONNECT LAYER USING TWO-DIMENSIONAL MATERIALS'
[patent_app_type] => utility
[patent_app_number] => 14/932439
[patent_app_country] => US
[patent_app_date] => 2015-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 6761
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14932439
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/932439 | Flexible device having flexible interconnect layer using two-dimensional materials | Nov 3, 2015 | Issued |