Search

Cam N Nguyen

Examiner (ID: 5643, Phone: (571)272-1357 , Office: P/1736 )

Most Active Art Unit
1736
Art Unit(s)
1736, 1793, 1754
Total Applications
2328
Issued Applications
1758
Pending Applications
181
Abandoned Applications
389

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6372162 [patent_doc_number] => 20100075475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'METHOD FOR PRODUCING A THIN FILM TRANSISTOR AND METHOD FOR FORMING AN ELECTRODE' [patent_app_type] => utility [patent_app_number] => 12/630245 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8983 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20100075475.pdf [firstpage_image] =>[orig_patent_app_number] => 12630245 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630245
METHOD FOR PRODUCING A THIN FILM TRANSISTOR AND METHOD FOR FORMING AN ELECTRODE Dec 2, 2009 Abandoned
Array ( [id] => 6304807 [patent_doc_number] => 20100068829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM' [patent_app_type] => utility [patent_app_number] => 12/624081 [patent_app_country] => US [patent_app_date] => 2009-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 12112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20100068829.pdf [firstpage_image] =>[orig_patent_app_number] => 12624081 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/624081
MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM Nov 22, 2009 Abandoned
Array ( [id] => 7773952 [patent_doc_number] => 08119501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Method for separating a semiconductor wafer into individual semiconductor dies using an implanted impurity' [patent_app_type] => utility [patent_app_number] => 12/618936 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2998 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/119/08119501.pdf [firstpage_image] =>[orig_patent_app_number] => 12618936 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/618936
Method for separating a semiconductor wafer into individual semiconductor dies using an implanted impurity Nov 15, 2009 Issued
Array ( [id] => 9165981 [patent_doc_number] => 08591656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Compound semiconductor manufacturing device, compound semiconductor manufacturing method, and jig for manufacturing compound semiconductor' [patent_app_type] => utility [patent_app_number] => 13/126110 [patent_app_country] => US [patent_app_date] => 2009-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 9171 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13126110 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/126110
Compound semiconductor manufacturing device, compound semiconductor manufacturing method, and jig for manufacturing compound semiconductor Nov 3, 2009 Issued
Array ( [id] => 6047763 [patent_doc_number] => 20110207293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'METHOD OF PRODUCING A HYBRID SUBSTRATE HAVING A CONTINUOUS BURIED EECTRICALLY INSULATING LAYER' [patent_app_type] => utility [patent_app_number] => 13/125953 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8214 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20110207293.pdf [firstpage_image] =>[orig_patent_app_number] => 13125953 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/125953
Method of producing a hybrid substrate having a continuous buried electrically insulating layer Oct 28, 2009 Issued
Array ( [id] => 6473697 [patent_doc_number] => 20100041215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'METHODS FOR PREPARATION OF HIGH-PURITY POLYSILICON RODS USING A METALLIC CORE MEANS' [patent_app_type] => utility [patent_app_number] => 12/603072 [patent_app_country] => US [patent_app_date] => 2009-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20100041215.pdf [firstpage_image] =>[orig_patent_app_number] => 12603072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/603072
Methods for preparation of high-purity polysilicon rods using a metallic core means Oct 20, 2009 Issued
Array ( [id] => 6336408 [patent_doc_number] => 20100019316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'Method of fabricating super trench MOSFET including buried source electrode' [patent_app_type] => utility [patent_app_number] => 12/586906 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9073 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20100019316.pdf [firstpage_image] =>[orig_patent_app_number] => 12586906 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/586906
Method of fabricating super trench MOSFET including buried source electrode Sep 28, 2009 Abandoned
Array ( [id] => 6623618 [patent_doc_number] => 20100003777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'Quantum Photonic Imagers and Methods of Fabrication Thereof' [patent_app_type] => utility [patent_app_number] => 12/561121 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 21329 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20100003777.pdf [firstpage_image] =>[orig_patent_app_number] => 12561121 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561121
Quantum photonic imagers and methods of fabrication thereof Sep 15, 2009 Issued
Array ( [id] => 6605804 [patent_doc_number] => 20100002497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'SPACE AND PROCESS EFFICIENT MRAM' [patent_app_type] => utility [patent_app_number] => 12/557726 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20100002497.pdf [firstpage_image] =>[orig_patent_app_number] => 12557726 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557726
Space and process efficient MRAM Sep 10, 2009 Issued
Array ( [id] => 6597385 [patent_doc_number] => 20100062603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'SEMICONDUCTOR DEVICES SUITABLE FOR NARROW PITCH APPLICATIONS AND METHODS OF FABRICATION THEREOF' [patent_app_type] => utility [patent_app_number] => 12/558370 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13428 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20100062603.pdf [firstpage_image] =>[orig_patent_app_number] => 12558370 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558370
Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof Sep 10, 2009 Issued
Array ( [id] => 6021390 [patent_doc_number] => 20110049716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'STRUCTURES OF AND METHODS AND TOOLS FOR FORMING IN-SITU METALLIC/DIELECTRIC CAPS FOR INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 12/553265 [patent_app_country] => US [patent_app_date] => 2009-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5848 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20110049716.pdf [firstpage_image] =>[orig_patent_app_number] => 12553265 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/553265
Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects Sep 2, 2009 Issued
Array ( [id] => 4639477 [patent_doc_number] => 08017504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Transistor having a high-k metal gate stack and a compressively stressed channel' [patent_app_type] => utility [patent_app_number] => 12/552548 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6887 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/017/08017504.pdf [firstpage_image] =>[orig_patent_app_number] => 12552548 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/552548
Transistor having a high-k metal gate stack and a compressively stressed channel Sep 1, 2009 Issued
Array ( [id] => 6590943 [patent_doc_number] => 20100291728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'MANUFACTURING METHOD OF THE SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 12/552491 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2185 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20100291728.pdf [firstpage_image] =>[orig_patent_app_number] => 12552491 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/552491
MANUFACTURING METHOD OF THE SOLAR CELL Sep 1, 2009 Abandoned
Array ( [id] => 4495783 [patent_doc_number] => 07947589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'FinFET formation with a thermal oxide spacer hard mask formed from crystalline silicon layer' [patent_app_type] => utility [patent_app_number] => 12/552774 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/947/07947589.pdf [firstpage_image] =>[orig_patent_app_number] => 12552774 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/552774
FinFET formation with a thermal oxide spacer hard mask formed from crystalline silicon layer Sep 1, 2009 Issued
Array ( [id] => 9817520 [patent_doc_number] => 08927303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Method for manufacturing light-emitting diode' [patent_app_type] => utility [patent_app_number] => 12/552368 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2340 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12552368 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/552368
Method for manufacturing light-emitting diode Sep 1, 2009 Issued
Array ( [id] => 8457960 [patent_doc_number] => 08293626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/552493 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 49 [patent_no_of_words] => 15528 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12552493 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/552493
Method for manufacturing semiconductor device Sep 1, 2009 Issued
Array ( [id] => 8114541 [patent_doc_number] => 08158482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Asymmetric transistor devices formed by asymmetric spacers and tilted implantation' [patent_app_type] => utility [patent_app_number] => 12/552333 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 8942 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/158/08158482.pdf [firstpage_image] =>[orig_patent_app_number] => 12552333 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/552333
Asymmetric transistor devices formed by asymmetric spacers and tilted implantation Sep 1, 2009 Issued
Array ( [id] => 4476946 [patent_doc_number] => 07906396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-15 [patent_title] => 'Flash memory and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/552777 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3830 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/906/07906396.pdf [firstpage_image] =>[orig_patent_app_number] => 12552777 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/552777
Flash memory and method of fabricating the same Sep 1, 2009 Issued
Array ( [id] => 8165730 [patent_doc_number] => 08174074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Asymmetric embedded silicon germanium field effect transistor' [patent_app_type] => utility [patent_app_number] => 12/551804 [patent_app_country] => US [patent_app_date] => 2009-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3581 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/174/08174074.pdf [firstpage_image] =>[orig_patent_app_number] => 12551804 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/551804
Asymmetric embedded silicon germanium field effect transistor Aug 31, 2009 Issued
Array ( [id] => 6021268 [patent_doc_number] => 20110049594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'SILICON-ON-INSULATOR SUBSTRATE WITH BUILT-IN SUBSTRATE JUNCTION' [patent_app_type] => utility [patent_app_number] => 12/551797 [patent_app_country] => US [patent_app_date] => 2009-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20110049594.pdf [firstpage_image] =>[orig_patent_app_number] => 12551797 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/551797
Silicon-on-insulator substrate with built-in substrate junction Aug 31, 2009 Issued
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