Search

Cam N Nguyen

Examiner (ID: 5643, Phone: (571)272-1357 , Office: P/1736 )

Most Active Art Unit
1736
Art Unit(s)
1736, 1793, 1754
Total Applications
2328
Issued Applications
1758
Pending Applications
181
Abandoned Applications
389

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5404062 [patent_doc_number] => 20090239376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH INTERFACE BARRIER' [patent_app_type] => utility [patent_app_number] => 12/165111 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20090239376.pdf [firstpage_image] =>[orig_patent_app_number] => 12165111 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165111
Method for fabricating semiconductor device with interface barrier Jun 29, 2008 Issued
Array ( [id] => 4495695 [patent_doc_number] => 07947569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Method for producing a semiconductor including a foreign material layer' [patent_app_type] => utility [patent_app_number] => 12/164652 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 34 [patent_no_of_words] => 12769 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/947/07947569.pdf [firstpage_image] =>[orig_patent_app_number] => 12164652 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164652
Method for producing a semiconductor including a foreign material layer Jun 29, 2008 Issued
Array ( [id] => 5265066 [patent_doc_number] => 20090117751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'METHOD FOR FORMING RADICAL OXIDE LAYER AND METHOD FOR FORMING DUAL GATE OXIDE LAYER USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/163911 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1853 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20090117751.pdf [firstpage_image] =>[orig_patent_app_number] => 12163911 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/163911
METHOD FOR FORMING RADICAL OXIDE LAYER AND METHOD FOR FORMING DUAL GATE OXIDE LAYER USING THE SAME Jun 26, 2008 Abandoned
Array ( [id] => 5452799 [patent_doc_number] => 20090068836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'METHOD OF FORMING CONTACT PLUG OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/163901 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3631 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20090068836.pdf [firstpage_image] =>[orig_patent_app_number] => 12163901 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/163901
Method of forming contact plug of semiconductor device Jun 26, 2008 Issued
Array ( [id] => 5452796 [patent_doc_number] => 20090068833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'METHOD OF FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/163851 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2502 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20090068833.pdf [firstpage_image] =>[orig_patent_app_number] => 12163851 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/163851
METHOD OF FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE Jun 26, 2008 Abandoned
Array ( [id] => 5460053 [patent_doc_number] => 20090320253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Electrode Stack For Capacitive Device' [patent_app_type] => utility [patent_app_number] => 12/146668 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4121 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20090320253.pdf [firstpage_image] =>[orig_patent_app_number] => 12146668 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146668
Electrode stack for capacitive device Jun 25, 2008 Issued
Array ( [id] => 5310321 [patent_doc_number] => 20090017602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE FOR MICROELECTRONICS AND OPTOELECTRONICS' [patent_app_type] => utility [patent_app_number] => 12/144992 [patent_app_country] => US [patent_app_date] => 2008-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3525 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20090017602.pdf [firstpage_image] =>[orig_patent_app_number] => 12144992 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144992
Method for manufacturing a semiconductor-on-insulator substrate for microelectronics and optoelectronics Jun 23, 2008 Issued
Array ( [id] => 4663687 [patent_doc_number] => 20080254594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS' [patent_app_type] => utility [patent_app_number] => 12/143912 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9469 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20080254594.pdf [firstpage_image] =>[orig_patent_app_number] => 12143912 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/143912
Strained silicon CMOS on hybrid crystal orientations Jun 22, 2008 Issued
Array ( [id] => 5395091 [patent_doc_number] => 20090315154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 12/142251 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 3622 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315154.pdf [firstpage_image] =>[orig_patent_app_number] => 12142251 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/142251
Semiconductor with through-substrate interconnect Jun 18, 2008 Issued
Array ( [id] => 5395058 [patent_doc_number] => 20090315121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'STABLE STRESS DIELECTRIC LAYER' [patent_app_type] => utility [patent_app_number] => 12/141932 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4024 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315121.pdf [firstpage_image] =>[orig_patent_app_number] => 12141932 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/141932
STABLE STRESS DIELECTRIC LAYER Jun 18, 2008 Abandoned
Array ( [id] => 4852700 [patent_doc_number] => 20080318443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Plasma enhanced cyclic deposition method of metal silicon nitride film' [patent_app_type] => utility [patent_app_number] => 12/157631 [patent_app_country] => US [patent_app_date] => 2008-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3773 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0318/20080318443.pdf [firstpage_image] =>[orig_patent_app_number] => 12157631 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/157631
Plasma enhanced cyclic deposition method of metal silicon nitride film Jun 11, 2008 Abandoned
Array ( [id] => 211490 [patent_doc_number] => 07622396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-24 [patent_title] => 'Method of producing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/155625 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/622/07622396.pdf [firstpage_image] =>[orig_patent_app_number] => 12155625 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/155625
Method of producing a semiconductor device Jun 5, 2008 Issued
Array ( [id] => 121323 [patent_doc_number] => 07709276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Manufacturing method of a semiconductor device and substrate processing apparatus' [patent_app_type] => utility [patent_app_number] => 12/155221 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6328 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/709/07709276.pdf [firstpage_image] =>[orig_patent_app_number] => 12155221 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/155221
Manufacturing method of a semiconductor device and substrate processing apparatus May 29, 2008 Issued
Array ( [id] => 5303570 [patent_doc_number] => 20090298222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Method for manufacturing Chalcogenide devices' [patent_app_type] => utility [patent_app_number] => 12/154952 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7852 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20090298222.pdf [firstpage_image] =>[orig_patent_app_number] => 12154952 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/154952
Method for manufacturing Chalcogenide devices May 27, 2008 Abandoned
Array ( [id] => 4708114 [patent_doc_number] => 20080296640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'SOLID-STATE IMAGE PICKUP DEVICE, METHOD FOR MAKING SAME, AND IMAGE PICKUP APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/128102 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10256 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296640.pdf [firstpage_image] =>[orig_patent_app_number] => 12128102 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128102
Solid-state image pickup device, method for making same, and image pickup apparatus May 27, 2008 Issued
Array ( [id] => 5446526 [patent_doc_number] => 20090047752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Method for manufacturing photoelectric conversion device' [patent_app_type] => utility [patent_app_number] => 12/153721 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 22398 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20090047752.pdf [firstpage_image] =>[orig_patent_app_number] => 12153721 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/153721
Method for manufacturing photoelectric conversion device May 22, 2008 Issued
Array ( [id] => 5428643 [patent_doc_number] => 20090087953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Manufacturing process of leadframe-based BGA packages' [patent_app_type] => utility [patent_app_number] => 12/153451 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4507 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20090087953.pdf [firstpage_image] =>[orig_patent_app_number] => 12153451 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/153451
Manufacturing process of leadframe-based BGA packages May 18, 2008 Issued
Array ( [id] => 4711177 [patent_doc_number] => 20080299703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Film growth system and method' [patent_app_type] => utility [patent_app_number] => 12/151562 [patent_app_country] => US [patent_app_date] => 2008-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11422 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20080299703.pdf [firstpage_image] =>[orig_patent_app_number] => 12151562 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/151562
Film growth system and method May 6, 2008 Issued
Array ( [id] => 5558355 [patent_doc_number] => 20090269932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'Method for fabricating self-aligned complimentary pillar structures and wiring' [patent_app_type] => utility [patent_app_number] => 12/149151 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6015 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20090269932.pdf [firstpage_image] =>[orig_patent_app_number] => 12149151 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/149151
Method for fabricating self-aligned complementary pillar structures and wiring Apr 27, 2008 Issued
Array ( [id] => 5456060 [patent_doc_number] => 20090256212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC' [patent_app_type] => utility [patent_app_number] => 12/101762 [patent_app_country] => US [patent_app_date] => 2008-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6654 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20090256212.pdf [firstpage_image] =>[orig_patent_app_number] => 12101762 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/101762
Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric Apr 10, 2008 Issued
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