Search

Cameron J. Allen

Examiner (ID: 16560, Phone: (571)270-3164 , Office: P/1774 )

Most Active Art Unit
1774
Art Unit(s)
1774, 1779, 1709, 1797, 1778
Total Applications
1061
Issued Applications
785
Pending Applications
15
Abandoned Applications
266

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15199813 [patent_doc_number] => 10497407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Memory device and method of operating same [patent_app_type] => utility [patent_app_number] => 16/207009 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16207009 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/207009
Memory device and method of operating same Nov 29, 2018 Issued
Array ( [id] => 14508851 [patent_doc_number] => 20190198080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => FERROELECTRIC MEMORY DEVICE AND METHOD OF PROGRAMMING SAME [patent_app_type] => utility [patent_app_number] => 16/196335 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16196335 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/196335
FERROELECTRIC MEMORY DEVICE AND METHOD OF PROGRAMMING SAME Nov 19, 2018 Abandoned
Array ( [id] => 16653143 [patent_doc_number] => 10930334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Feedback field-effect electronic device using feedback loop operation and array circuit using feedback field-effect electronic device [patent_app_type] => utility [patent_app_number] => 16/181669 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7455 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181669
Feedback field-effect electronic device using feedback loop operation and array circuit using feedback field-effect electronic device Nov 5, 2018 Issued
Array ( [id] => 17224764 [patent_doc_number] => 11177274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Vertical non-volatile memory device, method of fabricating the same device, and electric-electronic system having the same device [patent_app_type] => utility [patent_app_number] => 16/177566 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 40 [patent_no_of_words] => 9542 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177566 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177566
Vertical non-volatile memory device, method of fabricating the same device, and electric-electronic system having the same device Oct 31, 2018 Issued
Array ( [id] => 14888631 [patent_doc_number] => 10424362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Memory device and data refreshing method thereof [patent_app_type] => utility [patent_app_number] => 16/177453 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5188 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177453
Memory device and data refreshing method thereof Oct 31, 2018 Issued
Array ( [id] => 14691091 [patent_doc_number] => 20190244661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => METHOD OF READING RESISTIVE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/167051 [patent_app_country] => US [patent_app_date] => 2018-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16167051 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/167051
Method of reading resistive memory device Oct 21, 2018 Issued
Array ( [id] => 14768591 [patent_doc_number] => 10395696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-27 [patent_title] => Double data rate memory [patent_app_type] => utility [patent_app_number] => 16/161699 [patent_app_country] => US [patent_app_date] => 2018-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4139 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16161699 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/161699
Double data rate memory Oct 15, 2018 Issued
Array ( [id] => 16707422 [patent_doc_number] => 10957364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Charge pump supply optimization and noise reduction method for logic systems [patent_app_type] => utility [patent_app_number] => 16/143105 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3555 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143105 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143105
Charge pump supply optimization and noise reduction method for logic systems Sep 25, 2018 Issued
Array ( [id] => 16958870 [patent_doc_number] => 11062747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Apparatus for adjusting delay of command signal path [patent_app_type] => utility [patent_app_number] => 16/143187 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2354 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143187
Apparatus for adjusting delay of command signal path Sep 25, 2018 Issued
Array ( [id] => 14508925 [patent_doc_number] => 20190198117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING IN THE SAME [patent_app_type] => utility [patent_app_number] => 16/141147 [patent_app_country] => US [patent_app_date] => 2018-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141147 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/141147
Nonvolatile memory device with intermediate switching transistors and programming method Sep 24, 2018 Issued
Array ( [id] => 14381363 [patent_doc_number] => 20190164594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/136895 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16136895 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/136895
Memory device and method with data input Sep 19, 2018 Issued
Array ( [id] => 14875493 [patent_doc_number] => 20190287988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/109365 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16109365 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/109365
Memory device with multiple layers Aug 21, 2018 Issued
Array ( [id] => 13581487 [patent_doc_number] => 20180342292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/057113 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057113 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057113
Semiconductor storage device Aug 6, 2018 Issued
Array ( [id] => 13542779 [patent_doc_number] => 20180322936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => METHOD FOR MANAGING DATA BLOCKS AND METHOD OF DATA MANAGEMENT FOR DATA STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/038145 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16038145 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/038145
Method for managing data blocks and method of data management for data storage device Jul 16, 2018 Issued
Array ( [id] => 14366453 [patent_doc_number] => 10304538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate [patent_app_type] => utility [patent_app_number] => 16/037898 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 8660 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 441 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037898 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/037898
Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate Jul 16, 2018 Issued
Array ( [id] => 16699701 [patent_doc_number] => 10950309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Semiconductor memory column decoder device and method [patent_app_type] => utility [patent_app_number] => 16/036578 [patent_app_country] => US [patent_app_date] => 2018-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9411 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16036578 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/036578
Semiconductor memory column decoder device and method Jul 15, 2018 Issued
Array ( [id] => 14475081 [patent_doc_number] => 20190189186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SUB-WORD LINE DRIVERS AND RELATED SEMICONDUCTOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/034604 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16034604 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/034604
SUB-WORD LINE DRIVERS AND RELATED SEMICONDUCTOR MEMORY DEVICES Jul 12, 2018 Abandoned
Array ( [id] => 13832119 [patent_doc_number] => 20190019544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => Memory Circuitry [patent_app_type] => utility [patent_app_number] => 16/035147 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035147 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/035147
Memory circuitry Jul 12, 2018 Issued
Array ( [id] => 14381377 [patent_doc_number] => 20190164601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => MEMORY DEVICE AND AN OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/034921 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16034921 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/034921
Memory device with read-write-read memory controller Jul 12, 2018 Issued
Array ( [id] => 16699692 [patent_doc_number] => 10950300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Lifetime mixed level non-volatile memory system [patent_app_type] => utility [patent_app_number] => 16/006299 [patent_app_country] => US [patent_app_date] => 2018-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3823 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16006299 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/006299
Lifetime mixed level non-volatile memory system Jun 11, 2018 Issued
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