Candace L. Bradford

Array ( [id] => 3826726 [patent_doc_number] => 05832276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Resolving processor and system bus address collision in a high-level cache' [patent_app_type] => 1 [patent_app_number] => 8/726947 [patent_app_country] => US [patent_app_date] => 1996-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10972 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832276.pdf [firstpage_image] =>[orig_patent_app_number] => 726947 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4019584 [patent_doc_number] => 05860100 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Pipelined flushing of a high level cache and invalidation of lower level caches' [patent_app_type] => 1 [patent_app_number] => 8/726949 [patent_app_country] => US [patent_app_date] => 1996-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11026 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860100.pdf [firstpage_image] =>[orig_patent_app_number] => 726949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3853074 [patent_doc_number] => 05761699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'System for adapting a computer system to different types of data storage disks for interchangeable use with a disk drive' [patent_app_type] => 1 [patent_app_number] => 8/719590 [patent_app_country] => US [patent_app_date] => 1996-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 9019 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 374 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761699.pdf [firstpage_image] =>[orig_patent_app_number] => 719590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3853513 [patent_doc_number] => 05761730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Control device for controlling a connection between an arithmetic processor and a main memory unit' [patent_app_type] => 1 [patent_app_number] => 8/697563 [patent_app_country] => US [patent_app_date] => 1996-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3256 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761730.pdf [firstpage_image] =>[orig_patent_app_number] => 697563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3800347 [patent_doc_number] => 05819305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Method and apparatus for configuring operating modes in a memory' [patent_app_type] => 1 [patent_app_number] => 8/703175 [patent_app_country] => US [patent_app_date] => 1996-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3499 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819305.pdf [firstpage_image] =>[orig_patent_app_number] => 703175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3853123 [patent_doc_number] => 05761703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Apparatus and method for dynamic memory refresh' [patent_app_type] => 1 [patent_app_number] => 8/698843 [patent_app_country] => US [patent_app_date] => 1996-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6290 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761703.pdf [firstpage_image] =>[orig_patent_app_number] => 698843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4032677 [patent_doc_number] => 05907863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Memory control unit using preloaded values to generate optimal timing of memory control sequences between different memory segments' [patent_app_type] => 1 [patent_app_number] => 8/698979 [patent_app_country] => US [patent_app_date] => 1996-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8679 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907863.pdf [firstpage_image] =>[orig_patent_app_number] => 698979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4011198 [patent_doc_number] => 05920898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Memory control unit providing optimal timing of memory control sequences between different memory segments by optimally selecting among a plurality of memory requests' [patent_app_type] => 1 [patent_app_number] => 8/698001 [patent_app_country] => US [patent_app_date] => 1996-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8713 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920898.pdf [firstpage_image] =>[orig_patent_app_number] => 698001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3765686 [patent_doc_number] => 05802585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Batched checking of shared memory accesses' [patent_app_type] => 1 [patent_app_number] => 8/682341 [patent_app_country] => US [patent_app_date] => 1996-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9097 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802585.pdf [firstpage_image] =>[orig_patent_app_number] => 682341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3853499 [patent_doc_number] => 05761729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Validation checking of shared memory accesses' [patent_app_type] => 1 [patent_app_number] => 8/672221 [patent_app_country] => US [patent_app_date] => 1996-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8984 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761729.pdf [firstpage_image] =>[orig_patent_app_number] => 672221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3758928 [patent_doc_number] => 05787480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Lock-up free data sharing' [patent_app_type] => 1 [patent_app_number] => 8/684281 [patent_app_country] => US [patent_app_date] => 1996-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9015 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787480.pdf [firstpage_image] =>[orig_patent_app_number] => 684281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3913389 [patent_doc_number] => 05835950 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Self-invalidation method for reducing coherence overheads in a bus-based shared-memory multiprocessor apparatus' [patent_app_type] => 1 [patent_app_number] => 8/679083 [patent_app_country] => US [patent_app_date] => 1996-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5168 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835950.pdf [firstpage_image] =>[orig_patent_app_number] => 679083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3833364 [patent_doc_number] => 05813029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Upgradeable cache circuit using high speed multiplexer' [patent_app_type] => 1 [patent_app_number] => 8/677267 [patent_app_country] => US [patent_app_date] => 1996-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3090 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/813/05813029.pdf [firstpage_image] =>[orig_patent_app_number] => 677267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3782190 [patent_doc_number] => 05845330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Using an intermediate storage medium in a database management system' [patent_app_type] => 1 [patent_app_number] => 8/674857 [patent_app_country] => US [patent_app_date] => 1996-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3463 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845330.pdf [firstpage_image] =>[orig_patent_app_number] => 674857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3871599 [patent_doc_number] => 05768510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Object-oriented system, method and article of manufacture for a client-server application enabler system' [patent_app_type] => 1 [patent_app_number] => 8/675235 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 25633 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768510.pdf [firstpage_image] =>[orig_patent_app_number] => 675235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4019460 [patent_doc_number] => 05860091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method and apparatus for efficient management of non-aligned I/O write request in high bandwidth raid applications' [patent_app_type] => 1 [patent_app_number] => 8/671863 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7523 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860091.pdf [firstpage_image] =>[orig_patent_app_number] => 671863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3815877 [patent_doc_number] => 05829038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Backward inquiry to lower level caches prior to the eviction of a modified line from a higher level cache in a microprocessor hierarchical cache structure' [patent_app_type] => 1 [patent_app_number] => 8/670253 [patent_app_country] => US [patent_app_date] => 1996-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2777 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/829/05829038.pdf [firstpage_image] =>[orig_patent_app_number] => 670253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3758734 [patent_doc_number] => 05787466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Multi-tier cache and method for implementing such a system' [patent_app_type] => 1 [patent_app_number] => 8/641653 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4068 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787466.pdf [firstpage_image] =>[orig_patent_app_number] => 641653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3853268 [patent_doc_number] => 05761714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Single-cycle multi-accessible interleaved cache' [patent_app_type] => 1 [patent_app_number] => 8/638263 [patent_app_country] => US [patent_app_date] => 1996-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3647 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761714.pdf [firstpage_image] =>[orig_patent_app_number] => 638263 [rel_patent_id] =>[rel_patent_doc_number] =>)