Search

Candice Chan

Examiner (ID: 3022, Phone: (571)272-9013 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
720
Issued Applications
475
Pending Applications
86
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20002376 [patent_doc_number] => 20250140598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE INCLUDING POWER DISTRIBUTION GRIDS [patent_app_type] => utility [patent_app_number] => 19/004133 [patent_app_country] => US [patent_app_date] => 2024-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 49071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19004133 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/004133
3D semiconductor device and structure including power distribution grids Dec 26, 2024 Issued
Array ( [id] => 20305408 [patent_doc_number] => 12451408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Package structures [patent_app_type] => utility [patent_app_number] => 18/772247 [patent_app_country] => US [patent_app_date] => 2024-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772247 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772247
Package structures Jul 13, 2024 Issued
Array ( [id] => 19546630 [patent_doc_number] => 20240363666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 18/771052 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771052 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771052
Semiconductor device and method of manufacturing the same, and electronic apparatus Jul 11, 2024 Issued
Array ( [id] => 19484042 [patent_doc_number] => 20240332084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => METHODS OF REDUCING PARASITIC CAPACITANCE IN SEMICONDUTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/738707 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738707 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/738707
Methods of reducing parasitic capacitance in semicondutor devices Jun 9, 2024 Issued
Array ( [id] => 20111608 [patent_doc_number] => 12362344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Semiconductor package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/736766 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18736766 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/736766
Semiconductor package and method of manufacturing the same Jun 6, 2024 Issued
Array ( [id] => 19436151 [patent_doc_number] => 20240304649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 18/668941 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 82231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668941 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668941
Solid-state imaging device and electronic apparatus May 19, 2024 Issued
Array ( [id] => 19384683 [patent_doc_number] => 20240274553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => INTERPOSER, METHOD FOR FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 18/643474 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643474 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643474
Interposer, method for fabricating the same, and semiconductor package having the same Apr 22, 2024 Issued
Array ( [id] => 19964945 [patent_doc_number] => 12334465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Semiconductor package and method of forming same [patent_app_type] => utility [patent_app_number] => 18/631900 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631900 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631900
Semiconductor package and method of forming same Apr 9, 2024 Issued
Array ( [id] => 19741403 [patent_doc_number] => 12218251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/626594 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 53 [patent_no_of_words] => 23871 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626594 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626594
Semiconductor device Apr 3, 2024 Issued
Array ( [id] => 19305888 [patent_doc_number] => 20240234468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 18/615151 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615151 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615151
Semiconductor device and method of manufacturing the same, and electronic apparatus Mar 24, 2024 Issued
Array ( [id] => 19901521 [patent_doc_number] => 12279474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => OLED panel lower part protection film, and organic light-emitting display apparatus comprising same [patent_app_type] => utility [patent_app_number] => 18/614499 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6557 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614499
OLED panel lower part protection film, and organic light-emitting display apparatus comprising same Mar 21, 2024 Issued
Array ( [id] => 19305798 [patent_doc_number] => 20240234378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHODS FOR ALIGNING DIES USING REGISTRATION MARKS [patent_app_type] => utility [patent_app_number] => 18/614583 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614583 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614583
SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHODS FOR ALIGNING DIES USING REGISTRATION MARKS Mar 21, 2024 Pending
Array ( [id] => 20375335 [patent_doc_number] => 12482779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Hybrid backside thermal structures for enhanced ic packages [patent_app_type] => utility [patent_app_number] => 18/593775 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 7701 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593775 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/593775
Hybrid backside thermal structures for enhanced ic packages Feb 29, 2024 Issued
Array ( [id] => 19221449 [patent_doc_number] => 20240186153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => UNDERFILL FILM FOR SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/438158 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438158 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438158
Underfill film for semiconductor package and method for manufacturing semiconductor package using the same Feb 8, 2024 Issued
Array ( [id] => 19305795 [patent_doc_number] => 20240234375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => METHOD OF FABRICATING SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/429471 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429471 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429471
Method of fabricating semiconductor package Jan 31, 2024 Issued
Array ( [id] => 19161181 [patent_doc_number] => 20240153888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SILICON NITRIDE METAL LAYER COVERS [patent_app_type] => utility [patent_app_number] => 18/414003 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414003 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/414003
SILICON NITRIDE METAL LAYER COVERS Jan 15, 2024 Pending
Array ( [id] => 19130957 [patent_doc_number] => 20240136310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => APPARATUS INCLUDING INTEGRATED SEGMENTS AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/402755 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402755 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402755
APPARATUS INCLUDING INTEGRATED SEGMENTS AND METHODS OF MANUFACTURING THE SAME Jan 2, 2024 Pending
Array ( [id] => 19116560 [patent_doc_number] => 20240128310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => SEMICONDUCTOR DEVICE HAVING SUPPORTER PATTERN [patent_app_type] => utility [patent_app_number] => 18/396302 [patent_app_country] => US [patent_app_date] => 2023-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18396302 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/396302
Semiconductor device having supporter pattern Dec 25, 2023 Issued
Array ( [id] => 19101073 [patent_doc_number] => 20240120301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => INTEGRATED CIRCUIT CHIP INCLUDING A PASSIVATION NITRIDE LAYER IN CONTACT WITH A HIGH VOLTAGE BONDING PAD AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 18/544747 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544747 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/544747
Integrated circuit chip including a passivation nitride layer in contact with a high voltage bonding pad and method of making Dec 18, 2023 Issued
Array ( [id] => 19054992 [patent_doc_number] => 20240096961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => Source/Drain Metal Contact and Formation Thereof [patent_app_type] => utility [patent_app_number] => 18/520996 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520996 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/520996
Source/drain metal contact and formation thereof Nov 27, 2023 Issued
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