Search

Candice Chan

Examiner (ID: 3022, Phone: (571)272-9013 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
720
Issued Applications
475
Pending Applications
86
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20080946 [patent_doc_number] => 12355024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Heterogenous integration scheme for III-V/Si and Si CMOS integrated circuits [patent_app_type] => utility [patent_app_number] => 17/650758 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 63 [patent_no_of_words] => 2886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650758 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650758
Heterogenous integration scheme for III-V/Si and Si CMOS integrated circuits Feb 10, 2022 Issued
Array ( [id] => 17615435 [patent_doc_number] => 20220157715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => DEVICES AND METHODS OF VERTICAL INTEGRATIONS OF SEMICONDUCTOR CHIPS, MAGNETIC CHIPS, AND LEAD FRAMES [patent_app_type] => utility [patent_app_number] => 17/667734 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4532 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17667734 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/667734
Devices and methods of vertical integrations of semiconductor chips, magnetic chips, and lead frames Feb 8, 2022 Issued
Array ( [id] => 18555336 [patent_doc_number] => 20230253353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => BONDED ASSEMBLY CONTAINING DIFFERENT SIZE OPPOSING BONDING PADS AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/667238 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17667238 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/667238
Bonded assembly containing different size opposing bonding pads and methods of forming the same Feb 7, 2022 Issued
Array ( [id] => 19842763 [patent_doc_number] => 12255163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Bond pads for semiconductor die assemblies and associated methods and systems [patent_app_type] => utility [patent_app_number] => 17/666437 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8822 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17666437 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/666437
Bond pads for semiconductor die assemblies and associated methods and systems Feb 6, 2022 Issued
Array ( [id] => 19376638 [patent_doc_number] => 12068218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Package structures [patent_app_type] => utility [patent_app_number] => 17/665608 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665608 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665608
Package structures Feb 6, 2022 Issued
Array ( [id] => 19670937 [patent_doc_number] => 12183708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Double resist structure for electrodeposition bonding [patent_app_type] => utility [patent_app_number] => 17/588404 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 16 [patent_no_of_words] => 12414 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588404
Double resist structure for electrodeposition bonding Jan 30, 2022 Issued
Array ( [id] => 19046739 [patent_doc_number] => 11935859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Chip structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/588185 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4015 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588185
Chip structure and manufacturing method thereof Jan 27, 2022 Issued
Array ( [id] => 18008623 [patent_doc_number] => 20220367390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => METHOD AND APPARATUS FOR IMPROVED WAFER COATING [patent_app_type] => utility [patent_app_number] => 17/574484 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574484 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574484
Method and apparatus for improved wafer coating Jan 11, 2022 Issued
Array ( [id] => 18500580 [patent_doc_number] => 20230223375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => PACKAGE COMPRISING SPACERS BETWEEN INTEGRATED DEVICES [patent_app_type] => utility [patent_app_number] => 17/574360 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574360 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574360
Package comprising spacers between integrated devices Jan 11, 2022 Issued
Array ( [id] => 20132320 [patent_doc_number] => 12374638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Passivation structure for metal pattern [patent_app_type] => utility [patent_app_number] => 17/574257 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 11471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574257
Passivation structure for metal pattern Jan 11, 2022 Issued
Array ( [id] => 18579006 [patent_doc_number] => 11735546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Selective micro device transfer to receiver substrate [patent_app_type] => utility [patent_app_number] => 17/569900 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 59 [patent_no_of_words] => 11373 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569900 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569900
Selective micro device transfer to receiver substrate Jan 5, 2022 Issued
Array ( [id] => 18579007 [patent_doc_number] => 11735547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Selective micro device transfer to receiver substrate [patent_app_type] => utility [patent_app_number] => 17/569918 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 59 [patent_no_of_words] => 11374 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569918 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569918
Selective micro device transfer to receiver substrate Jan 5, 2022 Issued
Array ( [id] => 18563053 [patent_doc_number] => 11728306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Selective micro device transfer to receiver substrate [patent_app_type] => utility [patent_app_number] => 17/569893 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 59 [patent_no_of_words] => 11375 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569893
Selective micro device transfer to receiver substrate Jan 5, 2022 Issued
Array ( [id] => 17566649 [patent_doc_number] => 20220130798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/569657 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 461 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569657
Semiconductor package Jan 5, 2022 Issued
Array ( [id] => 17825713 [patent_doc_number] => 11430667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => 3D semiconductor device and structure with bonding [patent_app_type] => utility [patent_app_number] => 17/567680 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 74 [patent_no_of_words] => 51027 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567680 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567680
3D semiconductor device and structure with bonding Jan 2, 2022 Issued
Array ( [id] => 18456336 [patent_doc_number] => 20230197618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => MULTILAYER GLASS SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/557585 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557585 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557585
MULTILAYER GLASS SUBSTRATE Dec 20, 2021 Pending
Array ( [id] => 17708693 [patent_doc_number] => 20220208701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => PRINTED PACKAGE AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/557372 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 45602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -38 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557372 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557372
Printed package and method of making the same Dec 20, 2021 Issued
Array ( [id] => 19048298 [patent_doc_number] => 11937429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus [patent_app_type] => utility [patent_app_number] => 17/556704 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3059 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556704 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/556704
Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus Dec 19, 2021 Issued
Array ( [id] => 17708675 [patent_doc_number] => 20220208683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/645092 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17645092 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/645092
Semiconductor device and method for manufacturing same Dec 19, 2021 Issued
Array ( [id] => 18977211 [patent_doc_number] => 20240057303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => SEMICONDUCTOR COOLING ARRANGEMENT WITH IMPROVED HEATSINK [patent_app_type] => utility [patent_app_number] => 18/269486 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18269486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/269486
SEMICONDUCTOR COOLING ARRANGEMENT WITH IMPROVED HEATSINK Dec 16, 2021 Pending
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