Search

Candice Chan

Examiner (ID: 15581, Phone: (571)272-9013 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
742
Issued Applications
487
Pending Applications
88
Abandoned Applications
187

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16904799 [patent_doc_number] => 20210183715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/908378 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908378 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/908378
Semiconductor module and semiconductor device Jun 21, 2020 Issued
Array ( [id] => 20375208 [patent_doc_number] => 12482652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Method for forming integrated circuit structures [patent_app_type] => utility [patent_app_number] => 17/624174 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6928 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17624174 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/624174
Method for forming integrated circuit structures Jun 18, 2020 Issued
Array ( [id] => 17956552 [patent_doc_number] => 11482667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Nonvolatile memory device having a resistance change layer and a plurality of electrode pattern layers [patent_app_type] => utility [patent_app_number] => 16/904825 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8993 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16904825 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/904825
Nonvolatile memory device having a resistance change layer and a plurality of electrode pattern layers Jun 17, 2020 Issued
Array ( [id] => 18533220 [patent_doc_number] => 20230238296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/918907 [patent_app_country] => US [patent_app_date] => 2020-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17918907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/918907
Semiconductor device including stop islands and method for manufacturing semiconductor device May 24, 2020 Issued
Array ( [id] => 16257446 [patent_doc_number] => 20200266821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => MULTIPLE VIA STRUCTURE FOR HIGH PERFORMANCE STANDARD CELLS [patent_app_type] => utility [patent_app_number] => 15/929520 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15929520 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/929520
Multiple via structure for high performance standard cells May 6, 2020 Issued
Array ( [id] => 18402168 [patent_doc_number] => 11664316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Semiconductor devices having penetration vias with portions having decreasing widths [patent_app_type] => utility [patent_app_number] => 16/849085 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6712 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/849085
Semiconductor devices having penetration vias with portions having decreasing widths Apr 14, 2020 Issued
Array ( [id] => 17210785 [patent_doc_number] => 11171162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Display device having scan lines of different lengths [patent_app_type] => utility [patent_app_number] => 16/839121 [patent_app_country] => US [patent_app_date] => 2020-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4999 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16839121 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/839121
Display device having scan lines of different lengths Apr 2, 2020 Issued
Array ( [id] => 17668571 [patent_doc_number] => 11362276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => High thermal stability SiO [patent_app_type] => utility [patent_app_number] => 16/833349 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 7353 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833349
High thermal stability SiO Mar 26, 2020 Issued
Array ( [id] => 16119769 [patent_doc_number] => 20200211907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES BY ETCHING ACTIVE FINS USING ETCHING MASKS [patent_app_type] => utility [patent_app_number] => 16/810937 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16810937 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/810937
Methods of manufacturing semiconductor devices by etching active fins using etching masks Mar 5, 2020 Issued
Array ( [id] => 16301087 [patent_doc_number] => 20200286810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => MOUNTING DEVICES FOR SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 16/812260 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16812260 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/812260
Mounting devices for semiconductor packages with a fixation mechanism Mar 5, 2020 Issued
Array ( [id] => 16418014 [patent_doc_number] => 10825916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Vertical transport field-effect transistor including dual layer top spacer [patent_app_type] => utility [patent_app_number] => 16/746927 [patent_app_country] => US [patent_app_date] => 2020-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7424 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746927 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746927
Vertical transport field-effect transistor including dual layer top spacer Jan 18, 2020 Issued
Array ( [id] => 18514675 [patent_doc_number] => 20230230936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => WAFER AND METHOD OF MAKING, AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/040954 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17040954 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/040954
WAFER AND METHOD OF MAKING, AND SEMICONDUCTOR DEVICE Jan 15, 2020 Pending
Array ( [id] => 15906079 [patent_doc_number] => 20200152560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/739913 [patent_app_country] => US [patent_app_date] => 2020-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16739913 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/739913
Semiconductor device having passivation layer and method of manufacturing the same Jan 9, 2020 Issued
Array ( [id] => 19374207 [patent_doc_number] => 12065760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Method of manufacturing semiconductor element, semiconductor element, and substrate [patent_app_type] => utility [patent_app_number] => 17/418359 [patent_app_country] => US [patent_app_date] => 2019-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5883 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17418359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/418359
Method of manufacturing semiconductor element, semiconductor element, and substrate Dec 24, 2019 Issued
Array ( [id] => 17332458 [patent_doc_number] => 11222926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Light emitting display device including conductivity improvement layer [patent_app_type] => utility [patent_app_number] => 16/725829 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 15708 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16725829 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/725829
Light emitting display device including conductivity improvement layer Dec 22, 2019 Issued
Array ( [id] => 17745701 [patent_doc_number] => 11393783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Dummy structure of stacked and bonded semiconductor device [patent_app_type] => utility [patent_app_number] => 16/723751 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723751 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723751
Dummy structure of stacked and bonded semiconductor device Dec 19, 2019 Issued
Array ( [id] => 19152088 [patent_doc_number] => 11976996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Micromechanical component for a capacitive pressure sensor device [patent_app_type] => utility [patent_app_number] => 17/282736 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4575 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17282736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/282736
Micromechanical component for a capacitive pressure sensor device Dec 17, 2019 Issued
Array ( [id] => 15746017 [patent_doc_number] => 20200111898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING THINNED FINS [patent_app_type] => utility [patent_app_number] => 16/707985 [patent_app_country] => US [patent_app_date] => 2019-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16707985 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/707985
Method for manufacturing semiconductor device having thinned fins Dec 8, 2019 Issued
Array ( [id] => 15775803 [patent_doc_number] => 20200118919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => DEVICES INCLUDING STAIR STEP STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/676817 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676817 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/676817
Devices including stair step structures adjacent substantially planar, vertically extending surfaces of a stack structure Nov 6, 2019 Issued
Array ( [id] => 17716773 [patent_doc_number] => 11380773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Ferroelectric memory device [patent_app_type] => utility [patent_app_number] => 16/670375 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 11058 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670375 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670375
Ferroelectric memory device Oct 30, 2019 Issued
Menu