
Candice Chan
Examiner (ID: 15581, Phone: (571)272-9013 , Office: P/2813 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813 |
| Total Applications | 742 |
| Issued Applications | 487 |
| Pending Applications | 88 |
| Abandoned Applications | 187 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12659980
[patent_doc_number] => 20180111826
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-26
[patent_title] => INERTIAL SENSOR
[patent_app_type] => utility
[patent_app_number] => 15/782937
[patent_app_country] => US
[patent_app_date] => 2017-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4782
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782937
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/782937 | Micro electromechanical systems (MEMS)inertial sensor | Oct 12, 2017 | Issued |
Array
(
[id] => 12645306
[patent_doc_number] => 20180106933
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-19
[patent_title] => OPTICAL DETECTOR DEVICE WITH PATTERNED GRAPHENE LAYER AND RELATED METHODS
[patent_app_type] => utility
[patent_app_number] => 15/782948
[patent_app_country] => US
[patent_app_date] => 2017-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18726
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782948
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/782948 | Optical detector device with patterned graphene layer and related methods | Oct 12, 2017 | Issued |
Array
(
[id] => 14110291
[patent_doc_number] => 20190096821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-28
[patent_title] => MANUFACTURING METHOD OF PACKAGE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 15/713717
[patent_app_country] => US
[patent_app_date] => 2017-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11625
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713717
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/713717 | Manufacturing method of package structure having conductive shield | Sep 24, 2017 | Issued |
Array
(
[id] => 14125731
[patent_doc_number] => 10249731
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-04-02
[patent_title] => Vertical FET with sharp junctions
[patent_app_type] => utility
[patent_app_number] => 15/713975
[patent_app_country] => US
[patent_app_date] => 2017-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 22
[patent_no_of_words] => 4712
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713975
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/713975 | Vertical FET with sharp junctions | Sep 24, 2017 | Issued |
Array
(
[id] => 14459661
[patent_doc_number] => 10325802
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-18
[patent_title] => Method for fabricating semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/712410
[patent_app_country] => US
[patent_app_date] => 2017-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 36
[patent_no_of_words] => 10480
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712410
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/712410 | Method for fabricating semiconductor device | Sep 21, 2017 | Issued |
Array
(
[id] => 14558497
[patent_doc_number] => 10347721
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-09
[patent_title] => Method to increase strain in a semiconductor region for forming a channel of the transistor
[patent_app_type] => utility
[patent_app_number] => 15/711549
[patent_app_country] => US
[patent_app_date] => 2017-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 19
[patent_no_of_words] => 7476
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15711549
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/711549 | Method to increase strain in a semiconductor region for forming a channel of the transistor | Sep 20, 2017 | Issued |
Array
(
[id] => 14785233
[patent_doc_number] => 20190267514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE INCLUDING SAME
[patent_app_type] => utility
[patent_app_number] => 16/331039
[patent_app_country] => US
[patent_app_date] => 2017-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23991
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16331039
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/331039 | Semiconductor device having layers including aluminum and semiconductor device package including same | Sep 12, 2017 | Issued |
Array
(
[id] => 18156421
[patent_doc_number] => 11569416
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-31
[patent_title] => Light emitting semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/331015
[patent_app_country] => US
[patent_app_date] => 2017-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 63
[patent_no_of_words] => 28600
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16331015
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/331015 | Light emitting semiconductor device | Sep 10, 2017 | Issued |
Array
(
[id] => 14333137
[patent_doc_number] => 10297597
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-21
[patent_title] => Composite isolation structures for a fin-type field effect transistor
[patent_app_type] => utility
[patent_app_number] => 15/689711
[patent_app_country] => US
[patent_app_date] => 2017-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 4872
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689711
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/689711 | Composite isolation structures for a fin-type field effect transistor | Aug 28, 2017 | Issued |
Array
(
[id] => 12188932
[patent_doc_number] => 20180047868
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-15
[patent_title] => 'III-NITRIDE LED WITH TUNNEL JUNCTION'
[patent_app_type] => utility
[patent_app_number] => 15/674077
[patent_app_country] => US
[patent_app_date] => 2017-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10449
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674077
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/674077 | III-nitride LED with tunnel junction | Aug 9, 2017 | Issued |
Array
(
[id] => 15388785
[patent_doc_number] => 10535591
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-14
[patent_title] => Semiconductor device and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 15/674104
[patent_app_country] => US
[patent_app_date] => 2017-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 6625
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674104
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/674104 | Semiconductor device and method of manufacturing the same | Aug 9, 2017 | Issued |
Array
(
[id] => 13146123
[patent_doc_number] => 10090402
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-10-02
[patent_title] => Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates
[patent_app_type] => utility
[patent_app_number] => 15/658835
[patent_app_country] => US
[patent_app_date] => 2017-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 49
[patent_no_of_words] => 10246
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 319
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15658835
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/658835 | Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates | Jul 24, 2017 | Issued |
Array
(
[id] => 13405353
[patent_doc_number] => 20180254219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-06
[patent_title] => METHODS OF MANUFACTURING FINFET SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 15/658964
[patent_app_country] => US
[patent_app_date] => 2017-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15562
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15658964
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/658964 | Methods of manufacturing finFET semiconductor devices | Jul 24, 2017 | Issued |
Array
(
[id] => 13709159
[patent_doc_number] => 20170365534
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-21
[patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 15/625464
[patent_app_country] => US
[patent_app_date] => 2017-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9764
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625464
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/625464 | Manufacturing method of semiconductor package | Jun 15, 2017 | Issued |
Array
(
[id] => 13609773
[patent_doc_number] => 20180356436
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-13
[patent_title] => HIGH FREQUENCY ACCELEROMETER HOUSING
[patent_app_type] => utility
[patent_app_number] => 15/618839
[patent_app_country] => US
[patent_app_date] => 2017-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4096
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15618839
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/618839 | High frequency accelerometer housing including circuit board disposed directly above support pad | Jun 8, 2017 | Issued |
Array
(
[id] => 11967296
[patent_doc_number] => 20170271449
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-21
[patent_title] => 'Cobalt Silicidation Process for Substrates Comprised with a Silicon-Germanium Layer'
[patent_app_type] => utility
[patent_app_number] => 15/613778
[patent_app_country] => US
[patent_app_date] => 2017-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3742
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613778
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/613778 | Cobalt silicidation process for substrates comprised with a silicon-germanium layer | Jun 4, 2017 | Issued |
Array
(
[id] => 14205613
[patent_doc_number] => 10269934
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-23
[patent_title] => Method for manufacturing tunnel field effect transistor
[patent_app_type] => utility
[patent_app_number] => 15/590243
[patent_app_country] => US
[patent_app_date] => 2017-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 75
[patent_no_of_words] => 5235
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15590243
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/590243 | Method for manufacturing tunnel field effect transistor | May 8, 2017 | Issued |
Array
(
[id] => 11854922
[patent_doc_number] => 20170229414
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-10
[patent_title] => 'Semiconductor Device and Method'
[patent_app_type] => utility
[patent_app_number] => 15/497785
[patent_app_country] => US
[patent_app_date] => 2017-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8994
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497785
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/497785 | Method for a stacked and bonded semiconductor device | Apr 25, 2017 | Issued |
Array
(
[id] => 14252779
[patent_doc_number] => 10276597
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-30
[patent_title] => Electro-optical device and electronic apparatus
[patent_app_type] => utility
[patent_app_number] => 15/497784
[patent_app_country] => US
[patent_app_date] => 2017-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 9677
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497784
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/497784 | Electro-optical device and electronic apparatus | Apr 25, 2017 | Issued |
Array
(
[id] => 14429705
[patent_doc_number] => 10319666
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-11
[patent_title] => Thermal interface material structures including protruding surface features to reduce thermal interface material migration
[patent_app_type] => utility
[patent_app_number] => 15/491312
[patent_app_country] => US
[patent_app_date] => 2017-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5585
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15491312
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/491312 | Thermal interface material structures including protruding surface features to reduce thermal interface material migration | Apr 18, 2017 | Issued |