
Candice Chan
Examiner (ID: 15581, Phone: (571)272-9013 , Office: P/2813 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813 |
| Total Applications | 742 |
| Issued Applications | 487 |
| Pending Applications | 88 |
| Abandoned Applications | 187 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8505334
[patent_doc_number] => 20120304742
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-06
[patent_title] => 'INTEGRATED CMOS POROUS SENSOR'
[patent_app_type] => utility
[patent_app_number] => 13/561447
[patent_app_country] => US
[patent_app_date] => 2012-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8054
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13561447
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/561447 | INTEGRATED CMOS POROUS SENSOR | Jul 29, 2012 | Abandoned |
Array
(
[id] => 8439619
[patent_doc_number] => 20120256236
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-11
[patent_title] => 'INTEGRATED CMOS POROUS SENSOR'
[patent_app_type] => utility
[patent_app_number] => 13/494392
[patent_app_country] => US
[patent_app_date] => 2012-06-12
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/494392 | INTEGRATED CMOS POROUS SENSOR | Jun 11, 2012 | Abandoned |
Array
(
[id] => 10093038
[patent_doc_number] => 09129868
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-08
[patent_title] => 'Mask level reduction for MOFET'
[patent_app_type] => utility
[patent_app_number] => 13/481781
[patent_app_country] => US
[patent_app_date] => 2012-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/481781 | Mask level reduction for MOFET | May 25, 2012 | Issued |
Array
(
[id] => 8335613
[patent_doc_number] => 20120202320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-09
[patent_title] => 'WAFER-LEVEL CHIP SCALE PACKAGING OF METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET\'S)'
[patent_app_type] => utility
[patent_app_number] => 13/452750
[patent_app_country] => US
[patent_app_date] => 2012-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 2485
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/452750 | WAFER-LEVEL CHIP SCALE PACKAGING OF METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET'S) | Apr 19, 2012 | Abandoned |
Array
(
[id] => 8277970
[patent_doc_number] => 20120171841
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-05
[patent_title] => 'BODY CONTACTED TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE'
[patent_app_type] => utility
[patent_app_number] => 13/420123
[patent_app_country] => US
[patent_app_date] => 2012-03-14
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/420123 | Body contacted transistor with reduced parasitic capacitance | Mar 13, 2012 | Issued |
Array
(
[id] => 8207683
[patent_doc_number] => 20120127793
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-24
[patent_title] => 'MEMORY ARRAYS'
[patent_app_type] => utility
[patent_app_number] => 13/359947
[patent_app_country] => US
[patent_app_date] => 2012-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0127/20120127793.pdf
[firstpage_image] =>[orig_patent_app_number] => 13359947
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/359947 | Memory arrays with rows of memory cells coupled to opposite sides of a control gate | Jan 26, 2012 | Issued |
Array
(
[id] => 8166357
[patent_doc_number] => 20120104549
[patent_country] => US
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[patent_title] => 'MEMORY DEVICE AND FABRICATION THEREOF'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2012-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 58
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[pdf_file] => publications/A1/0104/20120104549.pdf
[firstpage_image] =>[orig_patent_app_number] => 13342416
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/342416 | MEMORY DEVICE AND FABRICATION THEREOF | Jan 2, 2012 | Abandoned |
Array
(
[id] => 9286838
[patent_doc_number] => 08643169
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-04
[patent_title] => 'Semiconductor sensor device with over-molded lid'
[patent_app_type] => utility
[patent_app_number] => 13/292104
[patent_app_country] => US
[patent_app_date] => 2011-11-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/292104 | Semiconductor sensor device with over-molded lid | Nov 8, 2011 | Issued |
Array
(
[id] => 8486984
[patent_doc_number] => 20120286391
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-15
[patent_title] => 'SEMICONDUCTOR CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/291461
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/291461 | SEMICONDUCTOR CIRCUIT | Nov 7, 2011 | Abandoned |
Array
(
[id] => 8205178
[patent_doc_number] => 20120126352
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-24
[patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR CHIPS, MOUNTING METHOD AND SEMICONDUCTOR CHIP FOR VERTICAL MOUNTING ONTO CIRCUIT SUBSTRATES'
[patent_app_type] => utility
[patent_app_number] => 13/291278
[patent_app_country] => US
[patent_app_date] => 2011-11-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0126/20120126352.pdf
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Array
(
[id] => 8414369
[patent_doc_number] => 20120241870
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[patent_issue_date] => 2012-09-27
[patent_title] => 'Bipolar junction transistor with surface protection and manufacturing method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/373225 | Bipolar junction transistor with surface protection and manufacturing method thereof | Nov 7, 2011 | Abandoned |
Array
(
[id] => 10531373
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[patent_title] => 'Vertical DMOS-field effect transistor'
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Array
(
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Array
(
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Array
(
[id] => 8812036
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/291596 | Quantum capacitance graphene varactors and fabrication methods | Nov 7, 2011 | Issued |
Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/275436 | Nonvolatile semiconductor memory device including pillars buried inside through holes | Oct 17, 2011 | Issued |
Array
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/228451 | Dummy cell pattern for improving device thermal uniformity | Sep 8, 2011 | Issued |