Search

Candice Chan

Examiner (ID: 15581, Phone: (571)272-9013 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
742
Issued Applications
487
Pending Applications
88
Abandoned Applications
187

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8505334 [patent_doc_number] => 20120304742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'INTEGRATED CMOS POROUS SENSOR' [patent_app_type] => utility [patent_app_number] => 13/561447 [patent_app_country] => US [patent_app_date] => 2012-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8054 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13561447 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/561447
INTEGRATED CMOS POROUS SENSOR Jul 29, 2012 Abandoned
Array ( [id] => 8439619 [patent_doc_number] => 20120256236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'INTEGRATED CMOS POROUS SENSOR' [patent_app_type] => utility [patent_app_number] => 13/494392 [patent_app_country] => US [patent_app_date] => 2012-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5491 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13494392 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/494392
INTEGRATED CMOS POROUS SENSOR Jun 11, 2012 Abandoned
Array ( [id] => 10093038 [patent_doc_number] => 09129868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Mask level reduction for MOFET' [patent_app_type] => utility [patent_app_number] => 13/481781 [patent_app_country] => US [patent_app_date] => 2012-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4413 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13481781 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/481781
Mask level reduction for MOFET May 25, 2012 Issued
Array ( [id] => 8335613 [patent_doc_number] => 20120202320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'WAFER-LEVEL CHIP SCALE PACKAGING OF METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET\'S)' [patent_app_type] => utility [patent_app_number] => 13/452750 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2485 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13452750 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/452750
WAFER-LEVEL CHIP SCALE PACKAGING OF METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET'S) Apr 19, 2012 Abandoned
Array ( [id] => 8277970 [patent_doc_number] => 20120171841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'BODY CONTACTED TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE' [patent_app_type] => utility [patent_app_number] => 13/420123 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13420123 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/420123
Body contacted transistor with reduced parasitic capacitance Mar 13, 2012 Issued
Array ( [id] => 8207683 [patent_doc_number] => 20120127793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'MEMORY ARRAYS' [patent_app_type] => utility [patent_app_number] => 13/359947 [patent_app_country] => US [patent_app_date] => 2012-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3178 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20120127793.pdf [firstpage_image] =>[orig_patent_app_number] => 13359947 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/359947
Memory arrays with rows of memory cells coupled to opposite sides of a control gate Jan 26, 2012 Issued
Array ( [id] => 8166357 [patent_doc_number] => 20120104549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'MEMORY DEVICE AND FABRICATION THEREOF' [patent_app_type] => utility [patent_app_number] => 13/342416 [patent_app_country] => US [patent_app_date] => 2012-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 5488 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104549.pdf [firstpage_image] =>[orig_patent_app_number] => 13342416 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/342416
MEMORY DEVICE AND FABRICATION THEREOF Jan 2, 2012 Abandoned
Array ( [id] => 9286838 [patent_doc_number] => 08643169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Semiconductor sensor device with over-molded lid' [patent_app_type] => utility [patent_app_number] => 13/292104 [patent_app_country] => US [patent_app_date] => 2011-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 5065 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13292104 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/292104
Semiconductor sensor device with over-molded lid Nov 8, 2011 Issued
Array ( [id] => 8486984 [patent_doc_number] => 20120286391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'SEMICONDUCTOR CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/291461 [patent_app_country] => US [patent_app_date] => 2011-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13291461 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/291461
SEMICONDUCTOR CIRCUIT Nov 7, 2011 Abandoned
Array ( [id] => 8205178 [patent_doc_number] => 20120126352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR CHIPS, MOUNTING METHOD AND SEMICONDUCTOR CHIP FOR VERTICAL MOUNTING ONTO CIRCUIT SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 13/291278 [patent_app_country] => US [patent_app_date] => 2011-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2243 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126352.pdf [firstpage_image] =>[orig_patent_app_number] => 13291278 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/291278
METHOD FOR MANUFACTURING SEMICONDUCTOR CHIPS, MOUNTING METHOD AND SEMICONDUCTOR CHIP FOR VERTICAL MOUNTING ONTO CIRCUIT SUBSTRATES Nov 7, 2011 Abandoned
Array ( [id] => 8414369 [patent_doc_number] => 20120241870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'Bipolar junction transistor with surface protection and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 13/373225 [patent_app_country] => US [patent_app_date] => 2011-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2196 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13373225 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/373225
Bipolar junction transistor with surface protection and manufacturing method thereof Nov 7, 2011 Abandoned
Array ( [id] => 10531373 [patent_doc_number] => 09257517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Vertical DMOS-field effect transistor' [patent_app_type] => utility [patent_app_number] => 13/291344 [patent_app_country] => US [patent_app_date] => 2011-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2819 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13291344 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/291344
Vertical DMOS-field effect transistor Nov 7, 2011 Issued
Array ( [id] => 8205129 [patent_doc_number] => 20120126320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'METHOD FOR MANUFACTURING A MOS-FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/291289 [patent_app_country] => US [patent_app_date] => 2011-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3443 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20120126320.pdf [firstpage_image] =>[orig_patent_app_number] => 13291289 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/291289
METHOD FOR MANUFACTURING A MOS-FIELD EFFECT TRANSISTOR Nov 7, 2011 Abandoned
Array ( [id] => 8192691 [patent_doc_number] => 20120119185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'ACTIVE LAYER FOR SILICON LIGHT-EMITTING DEVICES AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/291954 [patent_app_country] => US [patent_app_date] => 2011-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4904 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20120119185.pdf [firstpage_image] =>[orig_patent_app_number] => 13291954 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/291954
ACTIVE LAYER FOR SILICON LIGHT-EMITTING DEVICES AND METHOD FOR MANUFACTURING THE SAME Nov 7, 2011 Abandoned
Array ( [id] => 8812036 [patent_doc_number] => 20130113081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'QUANTUM CAPACITANCE GRAPHENE VARACTORS AND FABRICATION METHODS' [patent_app_type] => utility [patent_app_number] => 13/291596 [patent_app_country] => US [patent_app_date] => 2011-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4954 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13291596 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/291596
Quantum capacitance graphene varactors and fabrication methods Nov 7, 2011 Issued
Array ( [id] => 8610131 [patent_doc_number] => 20130015443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/291088 [patent_app_country] => US [patent_app_date] => 2011-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2700 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13291088 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/291088
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Nov 6, 2011 Abandoned
Array ( [id] => 7782045 [patent_doc_number] => 20120043601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 13/275436 [patent_app_country] => US [patent_app_date] => 2011-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7072 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20120043601.pdf [firstpage_image] =>[orig_patent_app_number] => 13275436 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/275436
Nonvolatile semiconductor memory device including pillars buried inside through holes Oct 17, 2011 Issued
Array ( [id] => 8705447 [patent_doc_number] => 20130062736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'POST-POLYMER REVEALING OF THROUGH-SUBSTRATE VIA TIPS' [patent_app_type] => utility [patent_app_number] => 13/228594 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3712 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228594 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228594
POST-POLYMER REVEALING OF THROUGH-SUBSTRATE VIA TIPS Sep 8, 2011 Abandoned
Array ( [id] => 8036923 [patent_doc_number] => 20120068196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'SEMICONDUCTOR LIGHT-EMITTING DEVICE AND A METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/228648 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6948 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20120068196.pdf [firstpage_image] =>[orig_patent_app_number] => 13228648 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228648
SEMICONDUCTOR LIGHT-EMITTING DEVICE AND A METHOD OF MANUFACTURE THEREOF Sep 8, 2011 Abandoned
Array ( [id] => 8705418 [patent_doc_number] => 20130062707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'DUMMY CELL PATTERN FOR IMPROVING DEVICE THERMAL UNIFORMITY' [patent_app_type] => utility [patent_app_number] => 13/228451 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2905 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228451 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228451
Dummy cell pattern for improving device thermal uniformity Sep 8, 2011 Issued
Menu