Candice Chan

Array ( [id] => 5010936 [patent_doc_number] => 20070281415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/771916 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10677 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20070281415.pdf [firstpage_image] =>[orig_patent_app_number] => 11771916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8590630 [patent_doc_number] => 08348503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'System for active array temperature sensing and cooling' [patent_app_type] => utility [patent_app_number] => 11/764703 [patent_app_country] => US [patent_app_date] => 2007-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4514 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11764703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5199235 [patent_doc_number] => 20070298553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Thin Film Transistor and Method For Production Thereof' [patent_app_type] => utility [patent_app_number] => 11/763744 [patent_app_country] => US [patent_app_date] => 2007-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6398 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20070298553.pdf [firstpage_image] =>[orig_patent_app_number] => 11763744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5188689 [patent_doc_number] => 20070166998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'INTERCONNECTING PROCESS AND METHOD FOR FABRICATING COMPLEX DIELECTRIC BARRIER ALYER' [patent_app_type] => utility [patent_app_number] => 11/695509 [patent_app_country] => US [patent_app_date] => 2007-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2799 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20070166998.pdf [firstpage_image] =>[orig_patent_app_number] => 11695509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4737211 [patent_doc_number] => 20080230863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Methods and apparatus for manufacturing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/726051 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20080230863.pdf [firstpage_image] =>[orig_patent_app_number] => 11726051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5186021 [patent_doc_number] => 20070164328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Method of manufacturing semiconductor device and the semiconductor device manufactured by the method' [patent_app_type] => utility [patent_app_number] => 11/717765 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11950 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20070164328.pdf [firstpage_image] =>[orig_patent_app_number] => 11717765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11043416 [patent_doc_number] => 20160240372 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2016-08-18 [patent_title] => 'Cobalt silicidation process for substrates comprised with a silicon-germanium layer' [patent_app_type] => utility [patent_app_number] => 11/714416 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3673 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11714416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11043416 [patent_doc_number] => 20160240372 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2016-08-18 [patent_title] => 'Cobalt silicidation process for substrates comprised with a silicon-germanium layer' [patent_app_type] => utility [patent_app_number] => 11/714416 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3673 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11714416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11043416 [patent_doc_number] => 20160240372 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2016-08-18 [patent_title] => 'Cobalt silicidation process for substrates comprised with a silicon-germanium layer' [patent_app_type] => utility [patent_app_number] => 11/714416 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3673 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11714416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11043416 [patent_doc_number] => 20160240372 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2016-08-18 [patent_title] => 'Cobalt silicidation process for substrates comprised with a silicon-germanium layer' [patent_app_type] => utility [patent_app_number] => 11/714416 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3673 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11714416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5098666 [patent_doc_number] => 20070181926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Semiconductor devices and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/702616 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20070181926.pdf [firstpage_image] =>[orig_patent_app_number] => 11702616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4843308 [patent_doc_number] => 20080179716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'MULTILEVEL INTERCONNECTS STRUCTURE WITH SHIELDING FUNCTION AND FABRICATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/668436 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4501 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20080179716.pdf [firstpage_image] =>[orig_patent_app_number] => 11668436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4485951 [patent_doc_number] => 07884022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Multiple deposition for integration of spacers in pitch multiplication process' [patent_app_type] => utility [patent_app_number] => 11/625165 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7812 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884022.pdf [firstpage_image] =>[orig_patent_app_number] => 11625165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10073620 [patent_doc_number] => 09111985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-08-18 [patent_title] => 'Shallow bipolar junction transistor' [patent_app_type] => utility [patent_app_number] => 11/652785 [patent_app_country] => US [patent_app_date] => 2007-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3510 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11652785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4927474 [patent_doc_number] => 20080166837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Power MOSFET wafer level chip-scale package' [patent_app_type] => utility [patent_app_number] => 11/652385 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2336 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20080166837.pdf [firstpage_image] =>[orig_patent_app_number] => 11652385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4435181 [patent_doc_number] => 07898017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Floating-gate memory cell and memory device and electronic system therewith' [patent_app_type] => utility [patent_app_number] => 11/600357 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4261 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898017.pdf [firstpage_image] =>[orig_patent_app_number] => 11600357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4825871 [patent_doc_number] => 20080124835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'HERMETIC SEAL AND RELIABLE BONDING STRUCTURES FOR 3D APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 11/534366 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4062 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20080124835.pdf [firstpage_image] =>[orig_patent_app_number] => 11534366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5032098 [patent_doc_number] => 20070096637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Organic light-emitting display apparatus' [patent_app_type] => utility [patent_app_number] => 11/590999 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096637.pdf [firstpage_image] =>[orig_patent_app_number] => 11590999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5168827 [patent_doc_number] => 20070069258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Pixel having two semiconductor layers, image sensor including the pixel, and image processing system including the image sensor' [patent_app_type] => utility [patent_app_number] => 11/524695 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6338 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20070069258.pdf [firstpage_image] =>[orig_patent_app_number] => 11524695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4992296 [patent_doc_number] => 20070007640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Surface mount package' [patent_app_type] => utility [patent_app_number] => 11/521885 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 24325 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20070007640.pdf [firstpage_image] =>[orig_patent_app_number] => 11521885 [rel_patent_id] =>[rel_patent_doc_number] =>)