Search

Candice Chan

Examiner (ID: 1009, Phone: (571)272-9013 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
707
Issued Applications
472
Pending Applications
80
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5104442 [patent_doc_number] => 20070063317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Overlay key, method of forming the overlay key, semiconductor device including the overlay key and method of manufacturing the semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/472376 [patent_app_country] => US [patent_app_date] => 2006-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8079 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20070063317.pdf [firstpage_image] =>[orig_patent_app_number] => 11472376 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/472376
Overlay key, method of forming the overlay key, semiconductor device including the overlay key and method of manufacturing the semiconductor device Jun 21, 2006 Abandoned
Array ( [id] => 5093003 [patent_doc_number] => 20070114612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Method of fabricating semiconductor devices having MCFET/finFET and related device' [patent_app_type] => utility [patent_app_number] => 11/443816 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6860 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20070114612.pdf [firstpage_image] =>[orig_patent_app_number] => 11443816 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/443816
Method of fabricating semiconductor devices having MCFET/finFET and related device May 30, 2006 Abandoned
Array ( [id] => 5683047 [patent_doc_number] => 20060199317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'THIN FILM TRANSISTOR AND METHOD FOR PRODUCTION THEREOF' [patent_app_type] => utility [patent_app_number] => 11/420302 [patent_app_country] => US [patent_app_date] => 2006-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6469 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199317.pdf [firstpage_image] =>[orig_patent_app_number] => 11420302 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/420302
THIN FILM TRANSISTOR AND METHOD FOR PRODUCTION THEREOF May 24, 2006 Abandoned
Array ( [id] => 5222953 [patent_doc_number] => 20070252219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Memory cell array with low resistance common source and high current drivability' [patent_app_type] => utility [patent_app_number] => 11/412574 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 5665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20070252219.pdf [firstpage_image] =>[orig_patent_app_number] => 11412574 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/412574
Memory cell array with low resistance common source and high current drivability Apr 26, 2006 Issued
Array ( [id] => 196579 [patent_doc_number] => 07638392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Methods of forming capacitor structures' [patent_app_type] => utility [patent_app_number] => 11/406862 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 6416 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/638/07638392.pdf [firstpage_image] =>[orig_patent_app_number] => 11406862 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/406862
Methods of forming capacitor structures Apr 17, 2006 Issued
Array ( [id] => 5683070 [patent_doc_number] => 20060199340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Methods of implanting dopant into channel regions' [patent_app_type] => utility [patent_app_number] => 11/406863 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6373 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199340.pdf [firstpage_image] =>[orig_patent_app_number] => 11406863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/406863
Methods of implanting dopant into channel regions Apr 17, 2006 Issued
Array ( [id] => 5683071 [patent_doc_number] => 20060199341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Methods of forming threshold voltage implant regions' [patent_app_type] => utility [patent_app_number] => 11/406893 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6373 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199341.pdf [firstpage_image] =>[orig_patent_app_number] => 11406893 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/406893
Methods of forming threshold voltage implant regions Apr 17, 2006 Issued
Array ( [id] => 5649163 [patent_doc_number] => 20060134898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Semiconductor damascene trench and methods thereof' [patent_app_type] => utility [patent_app_number] => 11/348149 [patent_app_country] => US [patent_app_date] => 2006-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5750 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20060134898.pdf [firstpage_image] =>[orig_patent_app_number] => 11348149 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/348149
Semiconductor damascene trench and methods thereof Feb 5, 2006 Abandoned
Array ( [id] => 5694235 [patent_doc_number] => 20060154382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Capacitor with high dielectric constant materials and method of making' [patent_app_type] => utility [patent_app_number] => 11/346676 [patent_app_country] => US [patent_app_date] => 2006-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3962 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11346676 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/346676
Capacitor with high dielectric constant materials and method of making Feb 2, 2006 Abandoned
Array ( [id] => 5913097 [patent_doc_number] => 20060128159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Method of removing etch residues' [patent_app_type] => utility [patent_app_number] => 11/347445 [patent_app_country] => US [patent_app_date] => 2006-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2523 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20060128159.pdf [firstpage_image] =>[orig_patent_app_number] => 11347445 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/347445
Method of removing etch residues Feb 1, 2006 Abandoned
Array ( [id] => 4968636 [patent_doc_number] => 20070108638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'ALIGNMENT MARK WITH IMPROVED RESISTANCE TO DICING INDUCED CRACKING AND DELAMINATION IN THE SCRIBE REGION' [patent_app_type] => utility [patent_app_number] => 11/164266 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20070108638.pdf [firstpage_image] =>[orig_patent_app_number] => 11164266 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/164266
ALIGNMENT MARK WITH IMPROVED RESISTANCE TO DICING INDUCED CRACKING AND DELAMINATION IN THE SCRIBE REGION Nov 15, 2005 Abandoned
Array ( [id] => 5670334 [patent_doc_number] => 20060175688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/163556 [patent_app_country] => US [patent_app_date] => 2005-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20060175688.pdf [firstpage_image] =>[orig_patent_app_number] => 11163556 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163556
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM Oct 21, 2005 Abandoned
Array ( [id] => 92006 [patent_doc_number] => 07737003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Method and structure for optimizing yield of 3-D chip manufacture' [patent_app_type] => utility [patent_app_number] => 11/163226 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4974 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/737/07737003.pdf [firstpage_image] =>[orig_patent_app_number] => 11163226 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163226
Method and structure for optimizing yield of 3-D chip manufacture Oct 10, 2005 Issued
Array ( [id] => 5168871 [patent_doc_number] => 20070069302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method of fabricating CMOS devices having a single work function gate electrode by band gap engineering and article made thereby' [patent_app_type] => utility [patent_app_number] => 11/238445 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7992 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20070069302.pdf [firstpage_image] =>[orig_patent_app_number] => 11238445 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/238445
Method of fabricating CMOS devices having a single work function gate electrode by band gap engineering and article made thereby Sep 27, 2005 Abandoned
Array ( [id] => 9762227 [patent_doc_number] => 08846549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Method of forming bottom oxide for nitride flash memory' [patent_app_type] => utility [patent_app_number] => 11/235786 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2549 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11235786 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/235786
Method of forming bottom oxide for nitride flash memory Sep 26, 2005 Issued
Array ( [id] => 4974108 [patent_doc_number] => 20070215337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Heat Sink Material, Manufacturing Method For The Same, And Semiconductor Laser Device' [patent_app_type] => utility [patent_app_number] => 11/587036 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10765 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20070215337.pdf [firstpage_image] =>[orig_patent_app_number] => 11587036 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/587036
Heat Sink Material, Manufacturing Method For The Same, And Semiconductor Laser Device Sep 19, 2005 Abandoned
Array ( [id] => 5894993 [patent_doc_number] => 20060003532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Semiconductor device and method of manufacturing therefor' [patent_app_type] => utility [patent_app_number] => 11/221823 [patent_app_country] => US [patent_app_date] => 2005-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3876 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003532.pdf [firstpage_image] =>[orig_patent_app_number] => 11221823 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/221823
Semiconductor device and method of manufacturing therefor Sep 8, 2005 Abandoned
Array ( [id] => 5757338 [patent_doc_number] => 20060208283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/217295 [patent_app_country] => US [patent_app_date] => 2005-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20060208283.pdf [firstpage_image] =>[orig_patent_app_number] => 11217295 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/217295
Semiconductor device Sep 1, 2005 Abandoned
Array ( [id] => 307829 [patent_doc_number] => 07531903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Interconnection structure used in a pad region of a semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 11/218456 [patent_app_country] => US [patent_app_date] => 2005-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2713 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531903.pdf [firstpage_image] =>[orig_patent_app_number] => 11218456 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/218456
Interconnection structure used in a pad region of a semiconductor substrate Sep 1, 2005 Issued
Array ( [id] => 6978031 [patent_doc_number] => 20050287749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Methods for forming openings in doped silicon dioxide' [patent_app_type] => utility [patent_app_number] => 11/214225 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2365 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20050287749.pdf [firstpage_image] =>[orig_patent_app_number] => 11214225 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/214225
Methods for forming openings in doped silicon dioxide Aug 28, 2005 Abandoned
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