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Candice Chan

Examiner (ID: 15581, Phone: (571)272-9013 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
742
Issued Applications
487
Pending Applications
88
Abandoned Applications
187

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5823744 [patent_doc_number] => 20060060926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Semiconductor scheme for reduced circuit area in a simplified process' [patent_app_type] => utility [patent_app_number] => 10/944626 [patent_app_country] => US [patent_app_date] => 2004-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6894 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20060060926.pdf [firstpage_image] =>[orig_patent_app_number] => 10944626 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/944626
Semiconductor scheme for reduced circuit area in a simplified process Sep 16, 2004 Issued
Array ( [id] => 7116754 [patent_doc_number] => 20050070055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Thin film transistor and method for production thereof' [patent_app_type] => utility [patent_app_number] => 10/942066 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6405 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20050070055.pdf [firstpage_image] =>[orig_patent_app_number] => 10942066 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/942066
Thin film transistor and method for production thereof Sep 14, 2004 Abandoned
Array ( [id] => 5879813 [patent_doc_number] => 20060028895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Silver island anti-fuse' [patent_app_type] => utility [patent_app_number] => 10/914255 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5686 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20060028895.pdf [firstpage_image] =>[orig_patent_app_number] => 10914255 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914255
Silver island anti-fuse Aug 8, 2004 Abandoned
Array ( [id] => 5817951 [patent_doc_number] => 20060022264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Method of making a double gate semiconductor device with self-aligned gates and structure thereof' [patent_app_type] => utility [patent_app_number] => 10/909095 [patent_app_country] => US [patent_app_date] => 2004-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4852 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20060022264.pdf [firstpage_image] =>[orig_patent_app_number] => 10909095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/909095
Method of making a double gate semiconductor device with self-aligned gates and structure thereof Jul 29, 2004 Abandoned
Array ( [id] => 7323431 [patent_doc_number] => 20040251511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Semiconductor device including an isolation trench having a dopant barrier layer formed on a sidewall thereof and a method of manufacture therefor' [patent_app_type] => new [patent_app_number] => 10/884726 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3546 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20040251511.pdf [firstpage_image] =>[orig_patent_app_number] => 10884726 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/884726
Semiconductor device including an isolation trench having a dopant barrier layer formed on a sidewall thereof and a method of manufacture therefor Jul 1, 2004 Abandoned
Array ( [id] => 6994164 [patent_doc_number] => 20050133940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Method and structure for protecting an alignment mark' [patent_app_type] => utility [patent_app_number] => 10/865746 [patent_app_country] => US [patent_app_date] => 2004-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1618 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20050133940.pdf [firstpage_image] =>[orig_patent_app_number] => 10865746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/865746
Method and structure for protecting an alignment mark Jun 13, 2004 Abandoned
Array ( [id] => 7430010 [patent_doc_number] => 20040266173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Method for forming patterns for semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/859378 [patent_app_country] => US [patent_app_date] => 2004-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4438 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266173.pdf [firstpage_image] =>[orig_patent_app_number] => 10859378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/859378
Method for forming patterns for semiconductor devices Jun 1, 2004 Abandoned
Array ( [id] => 7364890 [patent_doc_number] => 20040092044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Ion current density measuring method and instrument, and semiconductor device manufacturing method' [patent_app_type] => new [patent_app_number] => 10/697326 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7430 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20040092044.pdf [firstpage_image] =>[orig_patent_app_number] => 10697326 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697326
Ion current density measuring method and instrument, and semiconductor device manufacturing method Oct 30, 2003 Abandoned
Array ( [id] => 7022957 [patent_doc_number] => 20050017351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Silicon on diamond wafers and devices' [patent_app_type] => utility [patent_app_number] => 10/610356 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6372 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017351.pdf [firstpage_image] =>[orig_patent_app_number] => 10610356 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/610356
Silicon on diamond wafers and devices Jun 29, 2003 Abandoned
Array ( [id] => 6680913 [patent_doc_number] => 20030116777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Novel low leakage current cascaded diode structure' [patent_app_type] => new [patent_app_number] => 10/357136 [patent_app_country] => US [patent_app_date] => 2003-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1919 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20030116777.pdf [firstpage_image] =>[orig_patent_app_number] => 10357136 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/357136
Novel low leakage current cascaded diode structure Feb 2, 2003 Abandoned
Array ( [id] => 6857968 [patent_doc_number] => 20030088976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Method and apparatus for gate blocking X-outs during a molding process' [patent_app_type] => new [patent_app_number] => 10/328476 [patent_app_country] => US [patent_app_date] => 2002-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3568 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20030088976.pdf [firstpage_image] =>[orig_patent_app_number] => 10328476 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/328476
Method and apparatus for gate blocking X-outs during a molding process Dec 23, 2002 Abandoned
Array ( [id] => 6813705 [patent_doc_number] => 20030073255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Novel self monitoring process for ultra thin gate oxidation' [patent_app_type] => new [patent_app_number] => 09/975257 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4130 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20030073255.pdf [firstpage_image] =>[orig_patent_app_number] => 09975257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975257
Novel self monitoring process for ultra thin gate oxidation Oct 11, 2001 Abandoned
Array ( [id] => 252570 [patent_doc_number] => 07579203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Light emitting device' [patent_app_type] => utility [patent_app_number] => 09/841156 [patent_app_country] => US [patent_app_date] => 2001-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 62 [patent_no_of_words] => 17888 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/579/07579203.pdf [firstpage_image] =>[orig_patent_app_number] => 09841156 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841156
Light emitting device Apr 24, 2001 Issued
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