Search

Candice Chan

Examiner (ID: 15581, Phone: (571)272-9013 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
742
Issued Applications
487
Pending Applications
88
Abandoned Applications
187

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18631857 [patent_doc_number] => 20230290762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => FLIP CHIP MICROLED AND CARTRIDGE ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 17/918720 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17918720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/918720
FLIP CHIP MICROLED AND CARTRIDGE ARRANGEMENT Apr 13, 2021 Pending
Array ( [id] => 17583008 [patent_doc_number] => 20220139863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => INTEGRATED CIRCUIT CHIP HAVING BS-PDN STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/228111 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17228111 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/228111
Integrated circuit chip having BS-PDN structure Apr 11, 2021 Issued
Array ( [id] => 16981177 [patent_doc_number] => 20210225414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => MRAM STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/224153 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/224153
MRAM structure with source lines having alternating branches at opposite sides and storage units in staggered arrangement Apr 6, 2021 Issued
Array ( [id] => 16951903 [patent_doc_number] => 20210210595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/209242 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209242
Semiconductor device containing an oxygen concentration distribution Mar 22, 2021 Issued
Array ( [id] => 18883019 [patent_doc_number] => 20240006388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => DISPLAY MODULE [patent_app_type] => utility [patent_app_number] => 18/271781 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18271781 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/271781
DISPLAY MODULE Mar 17, 2021 Pending
Array ( [id] => 17855107 [patent_doc_number] => 20220285150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => METHOD FOR FORMING CONTACT SURFACE ON TOP OF MESA STRUCTURE FORMED ON SEMICONDUCTOR SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/192233 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192233 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/192233
METHOD FOR FORMING CONTACT SURFACE ON TOP OF MESA STRUCTURE FORMED ON SEMICONDUCTOR SUBSTRATE Mar 3, 2021 Abandoned
Array ( [id] => 18859164 [patent_doc_number] => 11856774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Semiconductor memory device that includes a semiconductor column that penetrates a plurality of conductive layers [patent_app_type] => utility [patent_app_number] => 17/181027 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 36 [patent_no_of_words] => 15330 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181027 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181027
Semiconductor memory device that includes a semiconductor column that penetrates a plurality of conductive layers Feb 21, 2021 Issued
Array ( [id] => 18277155 [patent_doc_number] => 11616105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Display device structure for reducing defects [patent_app_type] => utility [patent_app_number] => 17/179825 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5426 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179825
Display device structure for reducing defects Feb 18, 2021 Issued
Array ( [id] => 18190691 [patent_doc_number] => 11581293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Light emitting device [patent_app_type] => utility [patent_app_number] => 17/169644 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11375 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169644 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169644
Light emitting device Feb 7, 2021 Issued
Array ( [id] => 19507830 [patent_doc_number] => 12119260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Methods for manufacturing semiconductor structures including isolation layer and semiconductor structures including isolation layer [patent_app_type] => utility [patent_app_number] => 17/428058 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3227 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17428058 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/428058
Methods for manufacturing semiconductor structures including isolation layer and semiconductor structures including isolation layer Feb 7, 2021 Issued
Array ( [id] => 18431664 [patent_doc_number] => 11676894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Resistance tunable fuse structure formed by embedded thin metal layers [patent_app_type] => utility [patent_app_number] => 17/166252 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8437 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166252 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/166252
Resistance tunable fuse structure formed by embedded thin metal layers Feb 2, 2021 Issued
Array ( [id] => 16858426 [patent_doc_number] => 20210159171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => STACKED VIA STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/165954 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165954 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165954
Stacked via structure Feb 2, 2021 Issued
Array ( [id] => 19370497 [patent_doc_number] => 12062591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Power semiconductor module with baseplate and heat dissipating element [patent_app_type] => utility [patent_app_number] => 17/159257 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 10182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/159257
Power semiconductor module with baseplate and heat dissipating element Jan 26, 2021 Issued
Array ( [id] => 19007955 [patent_doc_number] => 20240072026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME, AND SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/271849 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18271849 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/271849
SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME, AND SEMICONDUCTOR PACKAGE Jan 14, 2021 Pending
Array ( [id] => 16752641 [patent_doc_number] => 20210104653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => HOUSING COMPRISING A SEMICONDUCTOR BODY AND A METHOD FOR PRODUCING A HOUSING WITH A SEMICONDUCTOR BODY [patent_app_type] => utility [patent_app_number] => 17/126125 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126125 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126125
HOUSING COMPRISING A SEMICONDUCTOR BODY AND A METHOD FOR PRODUCING A HOUSING WITH A SEMICONDUCTOR BODY Dec 17, 2020 Abandoned
Array ( [id] => 19046723 [patent_doc_number] => 11935843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Physical unclonable functions with silicon-rich dielectric devices [patent_app_type] => utility [patent_app_number] => 17/112668 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6131 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112668 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112668
Physical unclonable functions with silicon-rich dielectric devices Dec 3, 2020 Issued
Array ( [id] => 19138055 [patent_doc_number] => 11973030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Layout structure of eFuse unit [patent_app_type] => utility [patent_app_number] => 16/952288 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1572 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952288 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/952288
Layout structure of eFuse unit Nov 18, 2020 Issued
Array ( [id] => 18205628 [patent_doc_number] => 11588036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => High-efficiency packaged chip structure and electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/095710 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5189 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095710 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095710
High-efficiency packaged chip structure and electronic device including the same Nov 10, 2020 Issued
Array ( [id] => 17599622 [patent_doc_number] => 20220149196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => GATE TRENCH POWER SEMICONDUCTOR DEVICES HAVING IMPROVED DEEP SHIELD CONNECTION PATTERNS [patent_app_type] => utility [patent_app_number] => 17/092923 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17092923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/092923
Gate trench power semiconductor devices having improved deep shield connection patterns Nov 8, 2020 Issued
Array ( [id] => 17448235 [patent_doc_number] => 20220068740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SEMICONDUCTOR SYSTEM AND METHOD OF FORMING SEMICONDUCTOR SYSTEM [patent_app_type] => utility [patent_app_number] => 17/088621 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17088621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/088621
SEMICONDUCTOR SYSTEM AND METHOD OF FORMING SEMICONDUCTOR SYSTEM Nov 3, 2020 Abandoned
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