Cara E. Rakowski

Array ( [id] => 14669919 [patent_doc_number] => 10372861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Method of macro placement and a non-transitory computer readable medium thereof [patent_app_type] => utility [patent_app_number] => 15/362700 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 2500 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12776260 [patent_doc_number] => 20180150588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => INTERCONNECT REUSE RESOLUTION WITH BUMP COMPENSATION IN A PACKAGE DESIGN [patent_app_type] => utility [patent_app_number] => 15/362346 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17106548 [patent_doc_number] => 11126766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => System and method for element quality improvement in 3D quadrilateral-dominant surface meshes [patent_app_type] => utility [patent_app_number] => 16/336641 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 11708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16336641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15285023 [patent_doc_number] => 10515176 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-24 [patent_title] => System and method for visualizing component data routes [patent_app_type] => utility [patent_app_number] => 15/298178 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 7703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15298178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12647829 [patent_doc_number] => 20180107774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => TIMING ANALYSIS FOR ELECTRONIC DESIGN AUTOMATION OF PARALLEL MULTI-STATE DRIVER CIRCUITS [patent_app_type] => utility [patent_app_number] => 15/297979 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14331351 [patent_doc_number] => 10296696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Semiconductor design assisting device and semiconductor design assisting method [patent_app_type] => utility [patent_app_number] => 15/296092 [patent_app_country] => US [patent_app_date] => 2016-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 37 [patent_no_of_words] => 13629 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 516 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15296092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11438288 [patent_doc_number] => 20170039309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'Transient IR-drop waveform measurement system and method for high speed integrated circuit' [patent_app_type] => utility [patent_app_number] => 15/297080 [patent_app_country] => US [patent_app_date] => 2016-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9215 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12647838 [patent_doc_number] => 20180107777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => OPTIMIZING AN INTEGRATED CIRCUIT (IC) DESIGN COMPRISING AT LEAST ONE WIDE-GATE OR WIDE-BUS [patent_app_type] => utility [patent_app_number] => 15/295837 [patent_app_country] => US [patent_app_date] => 2016-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15295837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11367506 [patent_doc_number] => 20170005487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'METHOD OF FORMING A BALANCING CIRCUIT FOR A PLURALITY OF BATTERY CELLS AND STRUCTURE THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/269587 [patent_app_country] => US [patent_app_date] => 2016-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8151 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15269587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11509456 [patent_doc_number] => 09600616 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-21 [patent_title] => 'Assuring chip reliability with automatic generation of drivers and assertions' [patent_app_type] => utility [patent_app_number] => 15/264336 [patent_app_country] => US [patent_app_date] => 2016-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15264336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17196500 [patent_doc_number] => 11165271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Control device and method for charging a non-aqueous rechargeable metal-air battery [patent_app_type] => utility [patent_app_number] => 16/312218 [patent_app_country] => US [patent_app_date] => 2016-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6790 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16312218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12174078 [patent_doc_number] => 09892222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-13 [patent_title] => 'Automated attribute propagation and hierarchical consistency checking for non-standard extensions' [patent_app_type] => utility [patent_app_number] => 15/234250 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4340 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11982426 [patent_doc_number] => 20170286580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'METHOD AND APPARATUS FOR CONFIGURING AN INTEGRATED CIRCUIT WITH A REQUESTED FEATURE SET' [patent_app_type] => utility [patent_app_number] => 15/234879 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5918 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12187136 [patent_doc_number] => 20180046072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'AUTOMATED FULL-CHIP DESIGN SPACE SAMPLING USING UNSUPERVISED MACHINE LEARNING' [patent_app_type] => utility [patent_app_number] => 15/233232 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16667524 [patent_doc_number] => 10936772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-02 [patent_title] => Methods for incremental circuit physical synthesis [patent_app_type] => utility [patent_app_number] => 15/233855 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11445451 [patent_doc_number] => 20170046472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'COMPUTER-READABLE STORAGE MEDIUM HAVING ELECTRO-STATIC DISCHARGE VERIFICATION PROGRAM STORED THEREIN, INFORMATION PROCESSING APPARATUS, AND METHOD OF VERIFYING ELECTRO-STATIC DISCHARGE' [patent_app_type] => utility [patent_app_number] => 15/231955 [patent_app_country] => US [patent_app_date] => 2016-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15231955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14365011 [patent_doc_number] => 10303812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Topography prediction using system state information [patent_app_type] => utility [patent_app_number] => 15/231487 [patent_app_country] => US [patent_app_date] => 2016-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15231487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11445450 [patent_doc_number] => 20170046471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'POLYGON-BASED GEOMETRY CLASSIFICATION FOR SEMICONDUCTOR MASK INSPECTION' [patent_app_type] => utility [patent_app_number] => 15/230836 [patent_app_country] => US [patent_app_date] => 2016-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15230836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12153838 [patent_doc_number] => 20180025101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'SYSTEMS AND METHOD FOR OPTIMIZING STATE ENCODING' [patent_app_type] => utility [patent_app_number] => 15/216302 [patent_app_country] => US [patent_app_date] => 2016-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15216302 [rel_patent_id] =>[rel_patent_doc_number] =>)