Search

Carib A. Oquendo

Examiner (ID: 9245, Phone: (571)270-7411 , Office: P/3678 )

Most Active Art Unit
3678
Art Unit(s)
3672, 3678
Total Applications
985
Issued Applications
735
Pending Applications
74
Abandoned Applications
188

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20208467 [patent_doc_number] => 20250278187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => CLUSTERED PARITY FOR NAND DATA PLACEMENT SCHEMA [patent_app_type] => utility [patent_app_number] => 19/212220 [patent_app_country] => US [patent_app_date] => 2025-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19212220 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/212220
CLUSTERED PARITY FOR NAND DATA PLACEMENT SCHEMA May 18, 2025 Pending
Array ( [id] => 20087135 [patent_doc_number] => 20250217071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => REDUCTION OF WRITE AMPLIFICATION IN SENSOR DATA RECORDERS [patent_app_type] => utility [patent_app_number] => 19/087368 [patent_app_country] => US [patent_app_date] => 2025-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19087368 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/087368
REDUCTION OF WRITE AMPLIFICATION IN SENSOR DATA RECORDERS Mar 20, 2025 Pending
Array ( [id] => 20659110 [patent_doc_number] => 20260111153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-23 [patent_title] => DATA STORAGE APPARATUS USING VIRTUAL ADDRESS, OPERATING METHOD THEREOF, AND MEMORY CONTROLLER THEREFOR [patent_app_type] => utility [patent_app_number] => 19/071558 [patent_app_country] => US [patent_app_date] => 2025-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19071558 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/071558
DATA STORAGE APPARATUS USING VIRTUAL ADDRESS, OPERATING METHOD THEREOF, AND MEMORY CONTROLLER THEREFOR Mar 4, 2025 Pending
Array ( [id] => 20520339 [patent_doc_number] => 20260044447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-12 [patent_title] => STORAGE DEVICE FOR READING DATA AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 19/063331 [patent_app_country] => US [patent_app_date] => 2025-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19063331 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/063331
STORAGE DEVICE FOR READING DATA AND METHOD OF OPERATING THE SAME Feb 25, 2025 Pending
Array ( [id] => 20520162 [patent_doc_number] => 20260044268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-12 [patent_title] => DATA PROTECTION METHOD AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 19/064515 [patent_app_country] => US [patent_app_date] => 2025-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19064515 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/064515
DATA PROTECTION METHOD AND STORAGE DEVICE Feb 25, 2025 Pending
Array ( [id] => 20051917 [patent_doc_number] => 20250190139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => ACCELERATED READ TRANSLATION PATH IN MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 19/057055 [patent_app_country] => US [patent_app_date] => 2025-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19057055 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/057055
ACCELERATED READ TRANSLATION PATH IN MEMORY SUB-SYSTEM Feb 18, 2025 Pending
Array ( [id] => 20043037 [patent_doc_number] => 20250181259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => BLOCK FAMILY-BASED ERROR AVOIDANCE FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 19/044005 [patent_app_country] => US [patent_app_date] => 2025-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19044005 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/044005
BLOCK FAMILY-BASED ERROR AVOIDANCE FOR MEMORY DEVICES Feb 2, 2025 Pending
Array ( [id] => 20249654 [patent_doc_number] => 20250298523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => SYSTEMS AND METHODS OF INCORPORATING ARTIFICIAL INTELLIGENCE ACCELERATORS ON MEMORY BASE DIES [patent_app_type] => utility [patent_app_number] => 19/038672 [patent_app_country] => US [patent_app_date] => 2025-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19038672 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/038672
SYSTEMS AND METHODS OF INCORPORATING ARTIFICIAL INTELLIGENCE ACCELERATORS ON MEMORY BASE DIES Jan 26, 2025 Pending
Array ( [id] => 20805051 [patent_doc_number] => 12669958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Supporting multiple active regions in memory devices [patent_app_type] => utility [patent_app_number] => 19/014824 [patent_app_country] => US [patent_app_date] => 2025-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19014824 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/014824
SUPPORTING MULTIPLE ACTIVE REGIONS IN MEMORY DEVICES Jan 8, 2025 Pending
Array ( [id] => 20351582 [patent_doc_number] => 20250348434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => TRANSFORMER ACCELERATION DEVICE [patent_app_type] => utility [patent_app_number] => 18/987158 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18987158 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/987158
TRANSFORMER ACCELERATION DEVICE Dec 18, 2024 Pending
Array ( [id] => 20070548 [patent_doc_number] => 20250208770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => ELECTRONIC DEVICE AND A METHOD FOR PROTECTING AN ASIL MEMORY AREA [patent_app_type] => utility [patent_app_number] => 18/987152 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18987152 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/987152
ELECTRONIC DEVICE AND A METHOD FOR PROTECTING AN ASIL MEMORY AREA Dec 18, 2024 Pending
Array ( [id] => 20166739 [patent_doc_number] => 20250258786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => SYSTEMS AND METHODS FOR TRANSMITTING AND RECEIVING DOUBLE DATA RATE (DDR) PHYSICAL (PHY) INTERFACE (DFI) SIGNALS USING UNIVERSAL CHIPLET INTERCONNECT EXPRESS (UCIe) [patent_app_type] => utility [patent_app_number] => 18/977225 [patent_app_country] => US [patent_app_date] => 2024-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977225 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/977225
SYSTEMS AND METHODS FOR TRANSMITTING AND RECEIVING DOUBLE DATA RATE (DDR) PHYSICAL (PHY) INTERFACE (DFI) SIGNALS USING UNIVERSAL CHIPLET INTERCONNECT EXPRESS (UCIe) Dec 10, 2024 Pending
Array ( [id] => 20758016 [patent_doc_number] => 12650785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Data transmission circuit, data transmission method, and electronic device [patent_app_type] => utility [patent_app_number] => 18/944310 [patent_app_country] => US [patent_app_date] => 2024-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 495 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18944310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/944310
Data transmission circuit, data transmission method, and electronic device Nov 11, 2024 Issued
Array ( [id] => 20365781 [patent_doc_number] => 20250355593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => STORAGE CONTROLLER, STORAGE DEVICE INCLUDING THE SAME AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/910826 [patent_app_country] => US [patent_app_date] => 2024-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18910826 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/910826
STORAGE CONTROLLER, STORAGE DEVICE INCLUDING THE SAME AND OPERATING METHOD THEREOF Oct 8, 2024 Pending
Array ( [id] => 20570364 [patent_doc_number] => 20260064288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => CYCLING OF MEMORY BLOCKS [patent_app_type] => utility [patent_app_number] => 18/817614 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18817614 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/817614
CYCLING OF MEMORY BLOCKS Aug 27, 2024 Pending
Array ( [id] => 19818892 [patent_doc_number] => 20250077099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/766990 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766990 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766990
Memory system and information processing system Jul 8, 2024 Issued
Array ( [id] => 20331376 [patent_doc_number] => 12461651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Data writing method, memory storage device and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 18/760055 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3585 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760055 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760055
Data writing method, memory storage device and memory control circuit unit Jun 30, 2024 Issued
Array ( [id] => 20408675 [patent_doc_number] => 20250377784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-11 [patent_title] => PARTIAL PAGE IN-PLACE REFRESH [patent_app_type] => utility [patent_app_number] => 18/737678 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18737678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/737678
PARTIAL PAGE IN-PLACE REFRESH Jun 6, 2024 Pending
Array ( [id] => 19633001 [patent_doc_number] => 20240411450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => METHOD AND APPARATUS FOR PERFORMING STORAGE SPACE MANAGEMENT OF MEMORY DEVICE WITH AID OF DYNAMIC BLOCK CONFIGURATION [patent_app_type] => utility [patent_app_number] => 18/668236 [patent_app_country] => US [patent_app_date] => 2024-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668236 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668236
Method and apparatus for performing storage space management of memory device with aid of dynamic block configuration May 18, 2024 Issued
Array ( [id] => 20481675 [patent_doc_number] => 12530150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Techniques for balancing write commands on solid state storage devices (SSDs) [patent_app_type] => utility [patent_app_number] => 18/639614 [patent_app_country] => US [patent_app_date] => 2024-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639614 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/639614
Techniques for balancing write commands on solid state storage devices (SSDs) Apr 17, 2024 Issued
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