Carl Dees

Array ( [id] => 20501060 [patent_doc_number] => 20260030521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => METHOD AND SYSTEM FOR GENERATING AT LEAST ONE PERSPECTIVE OF KNOWLEDGE GRAPH [patent_app_type] => utility [patent_app_number] => 19/277583 [patent_app_country] => US [patent_app_date] => 2025-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19277583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20043741 [patent_doc_number] => 20250181963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => SYSTEMS AND METHODS FOR AUDIO DATA AUGMENTATION [patent_app_type] => utility [patent_app_number] => 18/524950 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20010881 [patent_doc_number] => 20250149103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => DETERMINISTIC TEST PROGRAM GENERATION FOR EVALUATING CACHE COHERENCY [patent_app_type] => utility [patent_app_number] => 18/501111 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20403545 [patent_doc_number] => 12493518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Error correction using on-die parity bit storage and transitional signals [patent_app_type] => utility [patent_app_number] => 18/491308 [patent_app_country] => US [patent_app_date] => 2023-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18491308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19985700 [patent_doc_number] => 20250123922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => Non-Blocking Chipkill Recovery [patent_app_type] => utility [patent_app_number] => 18/486774 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18486774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18989788 [patent_doc_number] => 20240061757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => METHOD AND SYSTEM FOR ESTABLISHING DATA TRANSFER PROCESSES BETWEEN COMPONENTS OF A TEST SYSTEM [patent_app_type] => utility [patent_app_number] => 18/450293 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19568341 [patent_doc_number] => 12143124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Encoding and decoding method and related apparatus [patent_app_type] => utility [patent_app_number] => 18/366757 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 32 [patent_no_of_words] => 18289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18789062 [patent_doc_number] => 20230377675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => PULSE DETECTION IN MICROELECTRONIC DEVICES, AND RELATED DEVICES, SYSTEMS, AND METHODS [patent_app_type] => utility [patent_app_number] => 18/363587 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19748393 [patent_doc_number] => 20250036958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => TRAINING GENERATIVE NEURAL NETWORKS THROUGH REINFORCED SELF-TRAINING [patent_app_type] => utility [patent_app_number] => 18/358920 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18897238 [patent_doc_number] => 20240012723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => HIGH-RELIABILITY NON-VOLATILE MEMORY USING A VOTING MECHANISM [patent_app_type] => utility [patent_app_number] => 18/352744 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19530728 [patent_doc_number] => 20240354630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => Fault Tolerant Quantum Error Correction Using physical Transport of Qubits [patent_app_type] => utility [patent_app_number] => 18/347054 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19616570 [patent_doc_number] => 20240402250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => FAULT DETECTION IN PARALLEL HARDWARE [patent_app_type] => utility [patent_app_number] => 18/203258 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19865095 [patent_doc_number] => 20250103881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => METHOD, INFORMATION PROCESSING DEVICE, AND RECORDING MEDIUM STORING INSTRUCTIONS FOR SUPPORTING EVALUATION OF LEARNING PROCESS OF PREDICTION MODEL [patent_app_type] => utility [patent_app_number] => 18/561583 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18561583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20747205 [patent_doc_number] => 12647135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Fast efficient decoder for low distance RS and BCH codes [patent_app_type] => utility [patent_app_number] => 18/198636 [patent_app_country] => US [patent_app_date] => 2023-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7061 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18198636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18711726 [patent_doc_number] => 20230334355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SYSTEMS AND METHODS FOR DEGENERACY MITIGATION IN A QUANTUM PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/138989 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18681077 [patent_doc_number] => 20230318742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SELECTION CIRCUIT, TRANSCEIVER DEVICE, AND SELECTION METHOD [patent_app_type] => utility [patent_app_number] => 18/190123 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19405704 [patent_doc_number] => 20240289215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => Soft Decoding Error Prediction [patent_app_type] => utility [patent_app_number] => 18/175843 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18175843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18585061 [patent_doc_number] => 20230267325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => PROCESSING APPARATUS FOR NEURAL NETWORK CALCULATION AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/171125 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18321211 [patent_doc_number] => 20230119339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => BLOCK GROUP LOSS DETERMINING METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/068034 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19655109 [patent_doc_number] => 12176919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Error correction code circuit, memory device including error correction code circuit, and operation method of error correction code circuit [patent_app_type] => utility [patent_app_number] => 17/988140 [patent_app_country] => US [patent_app_date] => 2022-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 14992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17988140 [rel_patent_id] =>[rel_patent_doc_number] =>)