
Carl W. Whitehead Jr.
Examiner (ID: 6801)
| Most Active Art Unit | 2503 |
| Art Unit(s) | 2815, 2503, 2813 |
| Total Applications | 662 |
| Issued Applications | 472 |
| Pending Applications | 16 |
| Abandoned Applications | 174 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3594405
[patent_doc_number] => 05585674
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-17
[patent_title] => 'Transverse diffusion barrier interconnect structure'
[patent_app_type] => 1
[patent_app_number] => 8/557886
[patent_app_country] => US
[patent_app_date] => 1995-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 25
[patent_no_of_words] => 4523
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/585/05585674.pdf
[firstpage_image] =>[orig_patent_app_number] => 557886
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/557886 | Transverse diffusion barrier interconnect structure | Nov 13, 1995 | Issued |
Array
(
[id] => 3799402
[patent_doc_number] => 05780897
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'ESD protection clamp for mixed voltage I/O stages using NMOS transistors'
[patent_app_type] => 1
[patent_app_number] => 8/555463
[patent_app_country] => US
[patent_app_date] => 1995-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4375
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/780/05780897.pdf
[firstpage_image] =>[orig_patent_app_number] => 555463
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/555463 | ESD protection clamp for mixed voltage I/O stages using NMOS transistors | Nov 12, 1995 | Issued |
| 08/555393 | SCHOTTKY BARRIER DIODE HAVING A MESA STRUCTURE | Nov 8, 1995 | Abandoned |
Array
(
[id] => 3624639
[patent_doc_number] => 05614757
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-25
[patent_title] => 'Monolithic multilayer chip inductor having a no-connect terminal'
[patent_app_type] => 1
[patent_app_number] => 8/548555
[patent_app_country] => US
[patent_app_date] => 1995-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 3959
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/614/05614757.pdf
[firstpage_image] =>[orig_patent_app_number] => 548555
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/548555 | Monolithic multilayer chip inductor having a no-connect terminal | Oct 25, 1995 | Issued |
| 08/548933 | SEMICONDUCTOR DEVICE WITH A CARRIER BODY ON WHICH A SUBSTRATE WITH A SEMICONDUCTOR ELEMENT IS FASTENED BY MEANS OF A GLUE LAYER AND ON WHICH A PATTERN OF CONDUCTOR TRACKS IS FASTENED | Oct 25, 1995 | Abandoned |
Array
(
[id] => 3891289
[patent_doc_number] => 05714768
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Second-layer phase change memory array on top of a logic device'
[patent_app_type] => 1
[patent_app_number] => 8/547349
[patent_app_country] => US
[patent_app_date] => 1995-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 9082
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/714/05714768.pdf
[firstpage_image] =>[orig_patent_app_number] => 547349
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/547349 | Second-layer phase change memory array on top of a logic device | Oct 23, 1995 | Issued |
Array
(
[id] => 3736397
[patent_doc_number] => 05666003
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-09
[patent_title] => 'Packaged semiconductor device incorporating heat sink plate'
[patent_app_type] => 1
[patent_app_number] => 8/551925
[patent_app_country] => US
[patent_app_date] => 1995-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 36
[patent_no_of_words] => 6504
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/666/05666003.pdf
[firstpage_image] =>[orig_patent_app_number] => 551925
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/551925 | Packaged semiconductor device incorporating heat sink plate | Oct 22, 1995 | Issued |
Array
(
[id] => 3638081
[patent_doc_number] => 05610424
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-11
[patent_title] => 'Metal oxide semiconductor field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 8/546737
[patent_app_country] => US
[patent_app_date] => 1995-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 1185
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/610/05610424.pdf
[firstpage_image] =>[orig_patent_app_number] => 546737
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/546737 | Metal oxide semiconductor field effect transistor | Oct 22, 1995 | Issued |
Array
(
[id] => 3668711
[patent_doc_number] => 05598030
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Semiconductor device having multilevel tab leads'
[patent_app_type] => 1
[patent_app_number] => 8/546826
[patent_app_country] => US
[patent_app_date] => 1995-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 1514
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/598/05598030.pdf
[firstpage_image] =>[orig_patent_app_number] => 546826
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/546826 | Semiconductor device having multilevel tab leads | Oct 22, 1995 | Issued |
Array
(
[id] => 3736333
[patent_doc_number] => 05693982
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Semiconductor device socket'
[patent_app_type] => 1
[patent_app_number] => 8/545381
[patent_app_country] => US
[patent_app_date] => 1995-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 7288
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/693/05693982.pdf
[firstpage_image] =>[orig_patent_app_number] => 545381
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/545381 | Semiconductor device socket | Oct 18, 1995 | Issued |
Array
(
[id] => 3732608
[patent_doc_number] => 05652465
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-29
[patent_title] => 'Semiconductor device having dummy patterns and an upper insulating layer having cavities'
[patent_app_type] => 1
[patent_app_number] => 8/544589
[patent_app_country] => US
[patent_app_date] => 1995-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 3630
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/652/05652465.pdf
[firstpage_image] =>[orig_patent_app_number] => 544589
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/544589 | Semiconductor device having dummy patterns and an upper insulating layer having cavities | Oct 17, 1995 | Issued |
Array
(
[id] => 3665286
[patent_doc_number] => 05656858
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Semiconductor device with bump structure'
[patent_app_type] => 1
[patent_app_number] => 8/544637
[patent_app_country] => US
[patent_app_date] => 1995-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 6503
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/656/05656858.pdf
[firstpage_image] =>[orig_patent_app_number] => 544637
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/544637 | Semiconductor device with bump structure | Oct 17, 1995 | Issued |
Array
(
[id] => 3774397
[patent_doc_number] => 05734196
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-31
[patent_title] => 'Electronic packaging shaped beam lead fabrication'
[patent_app_type] => 1
[patent_app_number] => 8/542689
[patent_app_country] => US
[patent_app_date] => 1995-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2702
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/734/05734196.pdf
[firstpage_image] =>[orig_patent_app_number] => 542689
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/542689 | Electronic packaging shaped beam lead fabrication | Oct 12, 1995 | Issued |
Array
(
[id] => 3896091
[patent_doc_number] => 05834820
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-10
[patent_title] => 'Circuit for providing isolation of integrated circuit active areas'
[patent_app_type] => 1
[patent_app_number] => 8/543160
[patent_app_country] => US
[patent_app_date] => 1995-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2251
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/834/05834820.pdf
[firstpage_image] =>[orig_patent_app_number] => 543160
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/543160 | Circuit for providing isolation of integrated circuit active areas | Oct 12, 1995 | Issued |
Array
(
[id] => 3892832
[patent_doc_number] => 05777390
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Transparent and opaque metal-semiconductor-metal photodetectors'
[patent_app_type] => 1
[patent_app_number] => 8/541525
[patent_app_country] => US
[patent_app_date] => 1995-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 3698
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/777/05777390.pdf
[firstpage_image] =>[orig_patent_app_number] => 541525
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/541525 | Transparent and opaque metal-semiconductor-metal photodetectors | Oct 9, 1995 | Issued |
Array
(
[id] => 3799675
[patent_doc_number] => 05780916
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Asymmetric contacted metal-semiconductor-metal photodetectors'
[patent_app_type] => 1
[patent_app_number] => 8/541417
[patent_app_country] => US
[patent_app_date] => 1995-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 4061
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/780/05780916.pdf
[firstpage_image] =>[orig_patent_app_number] => 541417
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/541417 | Asymmetric contacted metal-semiconductor-metal photodetectors | Oct 9, 1995 | Issued |
Array
(
[id] => 3773977
[patent_doc_number] => 05817556
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'Method of manufacturing a semiconductor memory device including memory cells having connected source regions'
[patent_app_type] => 1
[patent_app_number] => 8/536173
[patent_app_country] => US
[patent_app_date] => 1995-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 4
[patent_no_of_words] => 3615
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 266
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/817/05817556.pdf
[firstpage_image] =>[orig_patent_app_number] => 536173
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/536173 | Method of manufacturing a semiconductor memory device including memory cells having connected source regions | Sep 28, 1995 | Issued |
Array
(
[id] => 3534443
[patent_doc_number] => 05583377
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'Pad array semiconductor device having a heat sink with die receiving cavity'
[patent_app_type] => 1
[patent_app_number] => 8/537169
[patent_app_country] => US
[patent_app_date] => 1995-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 5026
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/583/05583377.pdf
[firstpage_image] =>[orig_patent_app_number] => 537169
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/537169 | Pad array semiconductor device having a heat sink with die receiving cavity | Sep 28, 1995 | Issued |
Array
(
[id] => 3707358
[patent_doc_number] => 05675185
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'Semiconductor structure incorporating thin film transistors with undoped cap oxide layers'
[patent_app_type] => 1
[patent_app_number] => 8/537219
[patent_app_country] => US
[patent_app_date] => 1995-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 6803
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/675/05675185.pdf
[firstpage_image] =>[orig_patent_app_number] => 537219
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/537219 | Semiconductor structure incorporating thin film transistors with undoped cap oxide layers | Sep 28, 1995 | Issued |
Array
(
[id] => 3666141
[patent_doc_number] => 05648680
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'Lead-on-chip semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/536674
[patent_app_country] => US
[patent_app_date] => 1995-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 4319
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/648/05648680.pdf
[firstpage_image] =>[orig_patent_app_number] => 536674
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/536674 | Lead-on-chip semiconductor device | Sep 28, 1995 | Issued |