Carl W. Whitehead Jr.

Array ( [id] => 3629914 [patent_doc_number] => 05621239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'SOI device having a buried layer of reduced resistivity' [patent_app_type] => 1 [patent_app_number] => 8/475439 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 35 [patent_no_of_words] => 4571 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/621/05621239.pdf [firstpage_image] =>[orig_patent_app_number] => 475439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3624749 [patent_doc_number] => 05614765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Self aligned via dual damascene' [patent_app_type] => 1 [patent_app_number] => 8/478319 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 34 [patent_no_of_words] => 4850 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/614/05614765.pdf [firstpage_image] =>[orig_patent_app_number] => 478319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3706060 [patent_doc_number] => 05646452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Registration accuracy measurement mark for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/477835 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 6879 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646452.pdf [firstpage_image] =>[orig_patent_app_number] => 477835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3665202 [patent_doc_number] => 05656852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'High-dielectric-constant material electrodes comprising sidewall spacers' [patent_app_type] => 1 [patent_app_number] => 8/486565 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 4606 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656852.pdf [firstpage_image] =>[orig_patent_app_number] => 486565 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3666009 [patent_doc_number] => 05648670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Trench MOS-gated device with a minimum number of masks' [patent_app_type] => 1 [patent_app_number] => 8/474711 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4584 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/648/05648670.pdf [firstpage_image] =>[orig_patent_app_number] => 474711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3845728 [patent_doc_number] => 05744863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Chip carrier modules with heat sinks attached by flexible-epoxy' [patent_app_type] => 1 [patent_app_number] => 8/474341 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3310 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744863.pdf [firstpage_image] =>[orig_patent_app_number] => 474341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3686908 [patent_doc_number] => 05633531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Compression glass lead-in arrangement' [patent_app_type] => 1 [patent_app_number] => 8/477578 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4939 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633531.pdf [firstpage_image] =>[orig_patent_app_number] => 477578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3672111 [patent_doc_number] => 05600178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Semiconductor package having interdigitated leads' [patent_app_type] => 1 [patent_app_number] => 8/483675 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2744 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600178.pdf [firstpage_image] =>[orig_patent_app_number] => 483675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3627975 [patent_doc_number] => 05602423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Damascene conductors with embedded pillars' [patent_app_type] => 1 [patent_app_number] => 8/479989 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3320 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602423.pdf [firstpage_image] =>[orig_patent_app_number] => 479989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3513720 [patent_doc_number] => 05587605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Package for mating with a semiconductor die' [patent_app_type] => 1 [patent_app_number] => 8/473833 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2846 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587605.pdf [firstpage_image] =>[orig_patent_app_number] => 473833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3836434 [patent_doc_number] => 05814832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Electron emitting semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/478656 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3489 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/814/05814832.pdf [firstpage_image] =>[orig_patent_app_number] => 478656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3638011 [patent_doc_number] => 05610418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/468395 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 7374 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610418.pdf [firstpage_image] =>[orig_patent_app_number] => 468395 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3525852 [patent_doc_number] => 05489805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Slotted thermal dissipater for a semiconductor package' [patent_app_type] => 1 [patent_app_number] => 8/457794 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1376 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489805.pdf [firstpage_image] =>[orig_patent_app_number] => 457794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3652128 [patent_doc_number] => 05629558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Semiconductor diode integrated with bipolar/CMOS/DMOS technology' [patent_app_type] => 1 [patent_app_number] => 8/454647 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2245 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629558.pdf [firstpage_image] =>[orig_patent_app_number] => 454647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3747696 [patent_doc_number] => 05801397 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Device having a self-aligned gate electrode wrapped around the channel' [patent_app_type] => 1 [patent_app_number] => 8/452893 [patent_app_country] => US [patent_app_date] => 1995-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4117 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801397.pdf [firstpage_image] =>[orig_patent_app_number] => 452893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3694368 [patent_doc_number] => 05604379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Semiconductor device having external electrodes formed in concave portions of an anisotropic conductive film' [patent_app_type] => 1 [patent_app_number] => 8/452691 [patent_app_country] => US [patent_app_date] => 1995-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3795 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604379.pdf [firstpage_image] =>[orig_patent_app_number] => 452691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3896396 [patent_doc_number] => 05834840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Net-shape ceramic processing for electronic devices and packages' [patent_app_type] => 1 [patent_app_number] => 8/448725 [patent_app_country] => US [patent_app_date] => 1995-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 31040 [patent_no_of_claims] => 124 [patent_no_of_ind_claims] => 34 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834840.pdf [firstpage_image] =>[orig_patent_app_number] => 448725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3559382 [patent_doc_number] => 05543661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Semiconductor ceramic package with terminal vias' [patent_app_type] => 1 [patent_app_number] => 8/448855 [patent_app_country] => US [patent_app_date] => 1995-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 3247 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/543/05543661.pdf [firstpage_image] =>[orig_patent_app_number] => 448855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3515019 [patent_doc_number] => 05563442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Leadframe having exposed, solderable outer lead ends' [patent_app_type] => 1 [patent_app_number] => 8/449503 [patent_app_country] => US [patent_app_date] => 1995-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3362 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563442.pdf [firstpage_image] =>[orig_patent_app_number] => 449503 [rel_patent_id] =>[rel_patent_doc_number] =>)