| Application number | Title of the application | Filing Date | Status |
|---|
| 08/207149 | SEMICONDUCTOR DEVICE HAVING A MULTILAYER INTERCONNECTION STRUCTURE | Mar 7, 1994 | Abandoned |
Array
(
[id] => 3892704
[patent_doc_number] => 05723873
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-03
[patent_title] => 'Bilayer composite electrodes for diodes'
[patent_app_type] => 1
[patent_app_number] => 8/205519
[patent_app_country] => US
[patent_app_date] => 1994-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 7930
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/723/05723873.pdf
[firstpage_image] =>[orig_patent_app_number] => 205519
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/205519 | Bilayer composite electrodes for diodes | Mar 2, 1994 | Issued |
Array
(
[id] => 3628965
[patent_doc_number] => 05608259
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-04
[patent_title] => 'Reverse current flow prevention in a diffused resistor'
[patent_app_type] => 1
[patent_app_number] => 8/204718
[patent_app_country] => US
[patent_app_date] => 1994-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2676
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 339
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/608/05608259.pdf
[firstpage_image] =>[orig_patent_app_number] => 204718
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/204718 | Reverse current flow prevention in a diffused resistor | Mar 1, 1994 | Issued |
| 08/200832 | COPPER-SEMICONDUCTOR COMPOUNDS CAPABLE OF BEING PRODUCED AT ROOM TEMPERATURE | Feb 17, 1994 | Abandoned |
Array
(
[id] => 3463978
[patent_doc_number] => 05442237
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-15
[patent_title] => 'Semiconductor device having a low permittivity dielectric'
[patent_app_type] => 1
[patent_app_number] => 8/191736
[patent_app_country] => US
[patent_app_date] => 1994-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2256
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/442/05442237.pdf
[firstpage_image] =>[orig_patent_app_number] => 191736
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/191736 | Semiconductor device having a low permittivity dielectric | Feb 3, 1994 | Issued |
Array
(
[id] => 3423568
[patent_doc_number] => 05479052
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Contact structure with capacitor for group III-V semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/190525
[patent_app_country] => US
[patent_app_date] => 1994-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 24
[patent_no_of_words] => 4405
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479052.pdf
[firstpage_image] =>[orig_patent_app_number] => 190525
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/190525 | Contact structure with capacitor for group III-V semiconductor devices | Feb 1, 1994 | Issued |
Array
(
[id] => 3116059
[patent_doc_number] => 05414302
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-09
[patent_title] => 'Semiconductor device with a multilayered contact structure having a boro-phosphate silicate glass planarizing layer'
[patent_app_type] => 1
[patent_app_number] => 8/188113
[patent_app_country] => US
[patent_app_date] => 1994-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 13
[patent_no_of_words] => 2171
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/414/05414302.pdf
[firstpage_image] =>[orig_patent_app_number] => 188113
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/188113 | Semiconductor device with a multilayered contact structure having a boro-phosphate silicate glass planarizing layer | Jan 27, 1994 | Issued |
Array
(
[id] => 3124194
[patent_doc_number] => 05381033
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-10
[patent_title] => 'Dielectrics dividing wafer'
[patent_app_type] => 1
[patent_app_number] => 8/186890
[patent_app_country] => US
[patent_app_date] => 1994-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 16
[patent_no_of_words] => 5323
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/381/05381033.pdf
[firstpage_image] =>[orig_patent_app_number] => 186890
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/186890 | Dielectrics dividing wafer | Jan 26, 1994 | Issued |
Array
(
[id] => 3416685
[patent_doc_number] => 05444299
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-22
[patent_title] => 'Electronic package with lead wire connections'
[patent_app_type] => 1
[patent_app_number] => 8/186737
[patent_app_country] => US
[patent_app_date] => 1994-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2751
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/444/05444299.pdf
[firstpage_image] =>[orig_patent_app_number] => 186737
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/186737 | Electronic package with lead wire connections | Jan 24, 1994 | Issued |
Array
(
[id] => 3579904
[patent_doc_number] => 05523618
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'Electronic integrated circuit label'
[patent_app_type] => 1
[patent_app_number] => 8/185844
[patent_app_country] => US
[patent_app_date] => 1994-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 1443
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/523/05523618.pdf
[firstpage_image] =>[orig_patent_app_number] => 185844
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/185844 | Electronic integrated circuit label | Jan 24, 1994 | Issued |
Array
(
[id] => 3484719
[patent_doc_number] => 05457345
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-10
[patent_title] => 'Metallization composite having nickle intermediate/interface'
[patent_app_type] => 1
[patent_app_number] => 8/182310
[patent_app_country] => US
[patent_app_date] => 1994-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3647
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/457/05457345.pdf
[firstpage_image] =>[orig_patent_app_number] => 182310
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/182310 | Metallization composite having nickle intermediate/interface | Jan 13, 1994 | Issued |
Array
(
[id] => 3432275
[patent_doc_number] => 05455460
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-03
[patent_title] => 'Semiconductor device having complimentary bonding pads'
[patent_app_type] => 1
[patent_app_number] => 8/178344
[patent_app_country] => US
[patent_app_date] => 1994-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 1425
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/455/05455460.pdf
[firstpage_image] =>[orig_patent_app_number] => 178344
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/178344 | Semiconductor device having complimentary bonding pads | Jan 5, 1994 | Issued |
| 08/174771 | A SLOTTED THERMAL DISSIPATER FOR AN ELECTRONIC PACKAGE | Dec 28, 1993 | Abandoned |
Array
(
[id] => 3012604
[patent_doc_number] => 05355018
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-11
[patent_title] => 'Stress-free semiconductor leadframe'
[patent_app_type] => 1
[patent_app_number] => 8/174604
[patent_app_country] => US
[patent_app_date] => 1993-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2233
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/355/05355018.pdf
[firstpage_image] =>[orig_patent_app_number] => 174604
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/174604 | Stress-free semiconductor leadframe | Dec 27, 1993 | Issued |
| 08/169787 | TRANSVERSE DIFFUSION BARRIER INTERCONNECT STRUCTURE | Dec 19, 1993 | Abandoned |
Array
(
[id] => 3590571
[patent_doc_number] => 05552631
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'Semiconductor device assembly including power or ground plane which is provided on opposite surface of insulating layer from signal traces, and is exposed to central opening in insulating layer for interconnection to semiconductor die'
[patent_app_type] => 1
[patent_app_number] => 8/170138
[patent_app_country] => US
[patent_app_date] => 1993-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 25
[patent_no_of_words] => 17436
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/552/05552631.pdf
[firstpage_image] =>[orig_patent_app_number] => 170138
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/170138 | Semiconductor device assembly including power or ground plane which is provided on opposite surface of insulating layer from signal traces, and is exposed to central opening in insulating layer for interconnection to semiconductor die | Dec 19, 1993 | Issued |
Array
(
[id] => 3592280
[patent_doc_number] => 05550406
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Multi-layer tab tape having distinct signal, power and ground planes and wafer probe card with multi-layer substrate'
[patent_app_type] => 1
[patent_app_number] => 8/170136
[patent_app_country] => US
[patent_app_date] => 1993-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 29
[patent_no_of_words] => 18551
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/550/05550406.pdf
[firstpage_image] =>[orig_patent_app_number] => 170136
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/170136 | Multi-layer tab tape having distinct signal, power and ground planes and wafer probe card with multi-layer substrate | Dec 19, 1993 | Issued |
Array
(
[id] => 3954299
[patent_doc_number] => 05977628
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Semiconductor device mounted in resin sealed container'
[patent_app_type] => 1
[patent_app_number] => 8/168185
[patent_app_country] => US
[patent_app_date] => 1993-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 2591
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/977/05977628.pdf
[firstpage_image] =>[orig_patent_app_number] => 168185
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/168185 | Semiconductor device mounted in resin sealed container | Dec 16, 1993 | Issued |
Array
(
[id] => 3414232
[patent_doc_number] => 05461258
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-24
[patent_title] => 'Semiconductor device socket'
[patent_app_type] => 1
[patent_app_number] => 8/162951
[patent_app_country] => US
[patent_app_date] => 1993-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 7286
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/461/05461258.pdf
[firstpage_image] =>[orig_patent_app_number] => 162951
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/162951 | Semiconductor device socket | Dec 7, 1993 | Issued |
Array
(
[id] => 3413323
[patent_doc_number] => 05438224
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-01
[patent_title] => 'Integrated circuit package having a face-to-face IC chip arrangement'
[patent_app_type] => 1
[patent_app_number] => 8/159910
[patent_app_country] => US
[patent_app_date] => 1993-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 3616
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 277
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/438/05438224.pdf
[firstpage_image] =>[orig_patent_app_number] => 159910
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/159910 | Integrated circuit package having a face-to-face IC chip arrangement | Nov 30, 1993 | Issued |