Search

Carl W. Whitehead Jr.

Examiner (ID: 6801)

Most Active Art Unit
2503
Art Unit(s)
2815, 2503, 2813
Total Applications
662
Issued Applications
472
Pending Applications
16
Abandoned Applications
174

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3556694 [patent_doc_number] => 05493153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Plastic-packaged semiconductor device having a heat sink matched with a plastic package' [patent_app_type] => 1 [patent_app_number] => 8/157295 [patent_app_country] => US [patent_app_date] => 1993-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7742 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493153.pdf [firstpage_image] =>[orig_patent_app_number] => 157295 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/157295
Plastic-packaged semiconductor device having a heat sink matched with a plastic package Nov 25, 1993 Issued
Array ( [id] => 3529688 [patent_doc_number] => 05504375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Asymmetric studs and connecting lines to minimize stress' [patent_app_type] => 1 [patent_app_number] => 8/155492 [patent_app_country] => US [patent_app_date] => 1993-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2194 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504375.pdf [firstpage_image] =>[orig_patent_app_number] => 155492 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/155492
Asymmetric studs and connecting lines to minimize stress Nov 17, 1993 Issued
Array ( [id] => 3432311 [patent_doc_number] => 05455462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Plastic molded package with heat sink for integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 8/152935 [patent_app_country] => US [patent_app_date] => 1993-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 6149 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455462.pdf [firstpage_image] =>[orig_patent_app_number] => 152935 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/152935
Plastic molded package with heat sink for integrated circuit devices Nov 14, 1993 Issued
08/151590 FABRICATION METHOD USING OXIDATION TO CONTROL SIZE OF FUSIBLE LINK, AND STRUCTURE PRODUCIBLE BY THIS METHOD Nov 11, 1993 Abandoned
08/150253 SOI DEVICE HAVING A BURIED LAYER OF REDUCED RESISTIVITY Nov 9, 1993 Abandoned
Array ( [id] => 3033057 [patent_doc_number] => 05349217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Vacuum microelectronics device' [patent_app_type] => 1 [patent_app_number] => 8/144159 [patent_app_country] => US [patent_app_date] => 1993-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2806 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349217.pdf [firstpage_image] =>[orig_patent_app_number] => 144159 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/144159
Vacuum microelectronics device Oct 26, 1993 Issued
Array ( [id] => 3485454 [patent_doc_number] => 05406113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Bipolar transistor having a buried collector layer' [patent_app_type] => 1 [patent_app_number] => 8/136593 [patent_app_country] => US [patent_app_date] => 1993-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 5110 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/406/05406113.pdf [firstpage_image] =>[orig_patent_app_number] => 136593 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/136593
Bipolar transistor having a buried collector layer Oct 13, 1993 Issued
08/125357 CMOS TRANSISTOR WITH TWO-LAYER INVERSE-T TUNGSTEN GATE STRUCTURE Sep 20, 1993 Abandoned
08/123770 MONOLITHIC MICROWAVE INTEGRATED CIRCUIT ON HIGH RESISTIVITY SILICON Sep 19, 1993 Abandoned
Array ( [id] => 3432217 [patent_doc_number] => 05455456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Integrated circuit package lid' [patent_app_type] => 1 [patent_app_number] => 8/121677 [patent_app_country] => US [patent_app_date] => 1993-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4102 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455456.pdf [firstpage_image] =>[orig_patent_app_number] => 121677 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/121677
Integrated circuit package lid Sep 14, 1993 Issued
Array ( [id] => 3430047 [patent_doc_number] => 05416355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-16 [patent_title] => 'Semiconductor integrated circuit protectant incorporating cold cathode field emission' [patent_app_type] => 1 [patent_app_number] => 8/116216 [patent_app_country] => US [patent_app_date] => 1993-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 12126 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/416/05416355.pdf [firstpage_image] =>[orig_patent_app_number] => 116216 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/116216
Semiconductor integrated circuit protectant incorporating cold cathode field emission Sep 1, 1993 Issued
08/108766 ADVANCE MULTILAYER MOLDED PLASTIC PACKAGE USING MESIC TECHNOLOGY Aug 17, 1993 Abandoned
Array ( [id] => 3596316 [patent_doc_number] => 05521436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Semiconductor device with a foil-sealed lid' [patent_app_type] => 1 [patent_app_number] => 8/107309 [patent_app_country] => US [patent_app_date] => 1993-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3028 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521436.pdf [firstpage_image] =>[orig_patent_app_number] => 107309 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/107309
Semiconductor device with a foil-sealed lid Aug 16, 1993 Issued
Array ( [id] => 3061695 [patent_doc_number] => 05350942 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-27 [patent_title] => 'Low resistance silicided substrate contact' [patent_app_type] => 1 [patent_app_number] => 8/104386 [patent_app_country] => US [patent_app_date] => 1993-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 6738 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/350/05350942.pdf [firstpage_image] =>[orig_patent_app_number] => 104386 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/104386
Low resistance silicided substrate contact Aug 8, 1993 Issued
Array ( [id] => 3432243 [patent_doc_number] => 05455458 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Phase change cooling of semiconductor power modules' [patent_app_type] => 1 [patent_app_number] => 8/103647 [patent_app_country] => US [patent_app_date] => 1993-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2270 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455458.pdf [firstpage_image] =>[orig_patent_app_number] => 103647 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/103647
Phase change cooling of semiconductor power modules Aug 8, 1993 Issued
08/102963 INTEGRATED CIRCUIT PACKAGE HAVING A MULTILAYERED WIRING PORTION FORMED ON AN INSULATING SUBSTRATE Aug 5, 1993 Abandoned
Array ( [id] => 3420273 [patent_doc_number] => 05453638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Bonding and encapsulated three dimensional hybrid integrated circuit modules' [patent_app_type] => 1 [patent_app_number] => 8/102146 [patent_app_country] => US [patent_app_date] => 1993-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1702 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/453/05453638.pdf [firstpage_image] =>[orig_patent_app_number] => 102146 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/102146
Bonding and encapsulated three dimensional hybrid integrated circuit modules Aug 3, 1993 Issued
Array ( [id] => 3420279 [patent_doc_number] => 05394009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Tab semiconductor package with cushioned land grid array outer lead bumps' [patent_app_type] => 1 [patent_app_number] => 8/099617 [patent_app_country] => US [patent_app_date] => 1993-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1700 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/394/05394009.pdf [firstpage_image] =>[orig_patent_app_number] => 099617 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/099617
Tab semiconductor package with cushioned land grid array outer lead bumps Jul 29, 1993 Issued
08/099683 SEMICONDUCTOR DEVICE WITH DIAMOND HEAT DISSIPATION LAYER Jul 28, 1993 Pending
Array ( [id] => 3075541 [patent_doc_number] => 05360991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Integrated circuit devices with solderable lead frame' [patent_app_type] => 1 [patent_app_number] => 8/099118 [patent_app_country] => US [patent_app_date] => 1993-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4286 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/360/05360991.pdf [firstpage_image] =>[orig_patent_app_number] => 099118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/099118
Integrated circuit devices with solderable lead frame Jul 28, 1993 Issued
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