
Carl W. Whitehead Jr.
Examiner (ID: 6801)
| Most Active Art Unit | 2503 |
| Art Unit(s) | 2815, 2503, 2813 |
| Total Applications | 662 |
| Issued Applications | 472 |
| Pending Applications | 16 |
| Abandoned Applications | 174 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3933322
[patent_doc_number] => 05877548
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-02
[patent_title] => 'Terminal configuration in semiconductor IC device'
[patent_app_type] => 1
[patent_app_number] => 8/762005
[patent_app_country] => US
[patent_app_date] => 1996-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 6006
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/877/05877548.pdf
[firstpage_image] =>[orig_patent_app_number] => 762005
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/762005 | Terminal configuration in semiconductor IC device | Dec 10, 1996 | Issued |
Array
(
[id] => 3880009
[patent_doc_number] => 05825062
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Semiconductor device including a nonvolatile memory'
[patent_app_type] => 1
[patent_app_number] => 8/762769
[patent_app_country] => US
[patent_app_date] => 1996-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3022
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825062.pdf
[firstpage_image] =>[orig_patent_app_number] => 762769
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/762769 | Semiconductor device including a nonvolatile memory | Dec 9, 1996 | Issued |
Array
(
[id] => 4054034
[patent_doc_number] => 05869866
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions'
[patent_app_type] => 1
[patent_app_number] => 8/761401
[patent_app_country] => US
[patent_app_date] => 1996-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 5388
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/869/05869866.pdf
[firstpage_image] =>[orig_patent_app_number] => 761401
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761401 | Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions | Dec 5, 1996 | Issued |
Array
(
[id] => 3799488
[patent_doc_number] => 05780902
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Semiconductor device having LDD structure with pocket on drain side'
[patent_app_type] => 1
[patent_app_number] => 8/764105
[patent_app_country] => US
[patent_app_date] => 1996-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 3228
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/780/05780902.pdf
[firstpage_image] =>[orig_patent_app_number] => 764105
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/764105 | Semiconductor device having LDD structure with pocket on drain side | Dec 5, 1996 | Issued |
Array
(
[id] => 4054204
[patent_doc_number] => 05869879
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions'
[patent_app_type] => 1
[patent_app_number] => 8/761399
[patent_app_country] => US
[patent_app_date] => 1996-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 5028
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/869/05869879.pdf
[firstpage_image] =>[orig_patent_app_number] => 761399
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761399 | CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions | Dec 5, 1996 | Issued |
Array
(
[id] => 3811950
[patent_doc_number] => 05831281
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Thin film transistor'
[patent_app_type] => 1
[patent_app_number] => 8/757765
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 17
[patent_no_of_words] => 5576
[patent_no_of_claims] => 4
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[patent_words_short_claim] => 44
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/831/05831281.pdf
[firstpage_image] =>[orig_patent_app_number] => 757765
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757765 | Thin film transistor | Nov 26, 1996 | Issued |
Array
(
[id] => 3885630
[patent_doc_number] => 05798555
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Enhancement-depletion logic based on Ge mosfets'
[patent_app_type] => 1
[patent_app_number] => 8/756415
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 38
[patent_no_of_words] => 8643
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/798/05798555.pdf
[firstpage_image] =>[orig_patent_app_number] => 756415
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/756415 | Enhancement-depletion logic based on Ge mosfets | Nov 26, 1996 | Issued |
Array
(
[id] => 3776417
[patent_doc_number] => 05773898
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Hybrid integrated circuit with a spacer between the radiator plate and loading portion of the IC'
[patent_app_type] => 1
[patent_app_number] => 8/756649
[patent_app_country] => US
[patent_app_date] => 1996-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 22
[patent_no_of_words] => 2728
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/773/05773898.pdf
[firstpage_image] =>[orig_patent_app_number] => 756649
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/756649 | Hybrid integrated circuit with a spacer between the radiator plate and loading portion of the IC | Nov 25, 1996 | Issued |
Array
(
[id] => 3748417
[patent_doc_number] => 05801444
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Multilevel electronic structures containing copper layer and copper-semiconductor layers'
[patent_app_type] => 1
[patent_app_number] => 8/756829
[patent_app_country] => US
[patent_app_date] => 1996-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 41
[patent_no_of_words] => 5215
[patent_no_of_claims] => 14
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/801/05801444.pdf
[firstpage_image] =>[orig_patent_app_number] => 756829
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/756829 | Multilevel electronic structures containing copper layer and copper-semiconductor layers | Nov 19, 1996 | Issued |
Array
(
[id] => 3891863
[patent_doc_number] => 05714804
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Semiconductor contact structure in integrated semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/749083
[patent_app_country] => US
[patent_app_date] => 1996-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 4078
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/714/05714804.pdf
[firstpage_image] =>[orig_patent_app_number] => 749083
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/749083 | Semiconductor contact structure in integrated semiconductor devices | Nov 13, 1996 | Issued |
Array
(
[id] => 3885838
[patent_doc_number] => 05798570
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Plastic molded semiconductor package with thermal dissipation means'
[patent_app_type] => 1
[patent_app_number] => 8/749215
[patent_app_country] => US
[patent_app_date] => 1996-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 2331
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/798/05798570.pdf
[firstpage_image] =>[orig_patent_app_number] => 749215
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/749215 | Plastic molded semiconductor package with thermal dissipation means | Nov 13, 1996 | Issued |
Array
(
[id] => 3776099
[patent_doc_number] => 05773876
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Lead frame with electrostatic discharge protection'
[patent_app_type] => 1
[patent_app_number] => 8/744681
[patent_app_country] => US
[patent_app_date] => 1996-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4190
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/773/05773876.pdf
[firstpage_image] =>[orig_patent_app_number] => 744681
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/744681 | Lead frame with electrostatic discharge protection | Nov 5, 1996 | Issued |
Array
(
[id] => 3847453
[patent_doc_number] => 05708303
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'Semiconductor device having damascene interconnects'
[patent_app_type] => 1
[patent_app_number] => 8/742959
[patent_app_country] => US
[patent_app_date] => 1996-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3394
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/708/05708303.pdf
[firstpage_image] =>[orig_patent_app_number] => 742959
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/742959 | Semiconductor device having damascene interconnects | Oct 31, 1996 | Issued |
Array
(
[id] => 3892199
[patent_doc_number] => 05894156
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-13
[patent_title] => 'Semiconductor device having a high breakdown voltage isolation region'
[patent_app_type] => 1
[patent_app_number] => 8/739713
[patent_app_country] => US
[patent_app_date] => 1996-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 6115
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/894/05894156.pdf
[firstpage_image] =>[orig_patent_app_number] => 739713
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/739713 | Semiconductor device having a high breakdown voltage isolation region | Oct 28, 1996 | Issued |
Array
(
[id] => 3780666
[patent_doc_number] => 05757083
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Drain off-set for pull down transistor for low leakage SRAM\'s'
[patent_app_type] => 1
[patent_app_number] => 8/728090
[patent_app_country] => US
[patent_app_date] => 1996-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/757/05757083.pdf
[firstpage_image] =>[orig_patent_app_number] => 728090
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/728090 | Drain off-set for pull down transistor for low leakage SRAM's | Oct 8, 1996 | Issued |
Array
(
[id] => 3882631
[patent_doc_number] => 05747858
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Electronic component having an interconnect substrate adjacent to a side surface of a device substrate'
[patent_app_type] => 1
[patent_app_number] => 8/723817
[patent_app_country] => US
[patent_app_date] => 1996-09-30
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/747/05747858.pdf
[firstpage_image] =>[orig_patent_app_number] => 723817
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/723817 | Electronic component having an interconnect substrate adjacent to a side surface of a device substrate | Sep 29, 1996 | Issued |
Array
(
[id] => 3882458
[patent_doc_number] => 05804843
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Solid state pickup device for suppressing smear signals'
[patent_app_type] => 1
[patent_app_number] => 8/723131
[patent_app_country] => US
[patent_app_date] => 1996-09-30
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/804/05804843.pdf
[firstpage_image] =>[orig_patent_app_number] => 723131
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/723131 | Solid state pickup device for suppressing smear signals | Sep 29, 1996 | Issued |
Array
(
[id] => 3820796
[patent_doc_number] => 05789799
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'High frequency noise and impedance matched integrated circuits'
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[patent_app_number] => 8/727367
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[pdf_file] => patents/05/789/05789799.pdf
[firstpage_image] =>[orig_patent_app_number] => 727367
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/727367 | High frequency noise and impedance matched integrated circuits | Sep 26, 1996 | Issued |
Array
(
[id] => 3776000
[patent_doc_number] => 05850095
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-15
[patent_title] => 'ESD protection circuit using zener diode and interdigitated NPN transistor'
[patent_app_type] => 1
[patent_app_number] => 8/719195
[patent_app_country] => US
[patent_app_date] => 1996-09-24
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/850/05850095.pdf
[firstpage_image] =>[orig_patent_app_number] => 719195
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/719195 | ESD protection circuit using zener diode and interdigitated NPN transistor | Sep 23, 1996 | Issued |
Array
(
[id] => 3745251
[patent_doc_number] => 05753949
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Semiconductor device wherein one of capacitor electrodes comprises a conductor pole and conductor layer'
[patent_app_type] => 1
[patent_app_number] => 8/710939
[patent_app_country] => US
[patent_app_date] => 1996-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 24
[patent_no_of_words] => 7613
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/753/05753949.pdf
[firstpage_image] =>[orig_patent_app_number] => 710939
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/710939 | Semiconductor device wherein one of capacitor electrodes comprises a conductor pole and conductor layer | Sep 23, 1996 | Issued |