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Carla Shamee Mckinney

Examiner (ID: 15579)

Most Active Art Unit
2898
Art Unit(s)
2898
Total Applications
14
Issued Applications
0
Pending Applications
14
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13630019 [patent_doc_number] => 20180366562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES INCLUDING NOTCH WITHIN FIN FILLED WITH RARE EARTH OXIDE AND RELATED STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/627715 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627715 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627715
METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES INCLUDING NOTCH WITHIN FIN FILLED WITH RARE EARTH OXIDE AND RELATED STRUCTURE Jun 19, 2017 Abandoned
Array ( [id] => 16846146 [patent_doc_number] => 11018243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/627568 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 6209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15627568 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/627568
Semiconductor device and manufacturing method thereof Jun 19, 2017 Issued
Array ( [id] => 13695161 [patent_doc_number] => 20170358535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 15/617943 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617943 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617943
SEMICONDUCTOR PACKAGES Jun 7, 2017 Abandoned
Array ( [id] => 13598361 [patent_doc_number] => 20180350729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => METHOD AND FIXTURE FOR CHIP ATTACHMENT TO PHYSICAL OBJECTS [patent_app_type] => utility [patent_app_number] => 15/609108 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609108 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609108
Method and fixture for chip attachment to physical objects May 30, 2017 Issued
Array ( [id] => 13581835 [patent_doc_number] => 20180342466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/605450 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15605450 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/605450
Semiconductor device package and method of manufacturing the same May 24, 2017 Issued
Array ( [id] => 15985341 [patent_doc_number] => 10673010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Electroluminescent device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/574740 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4516 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15574740 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/574740
Electroluminescent device and manufacturing method thereof May 22, 2017 Issued
Array ( [id] => 13485611 [patent_doc_number] => 20180294348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL ON A RECESSED FIN IN THE SOURCE/DRAIN REGIONS OF A FINFET DEVICE [patent_app_type] => utility [patent_app_number] => 15/483476 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15483476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/483476
Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device Apr 9, 2017 Issued
Array ( [id] => 15547657 [patent_doc_number] => 10573619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Printed wiring board [patent_app_type] => utility [patent_app_number] => 15/477589 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6951 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477589 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477589
Printed wiring board Apr 2, 2017 Issued
Array ( [id] => 14460057 [patent_doc_number] => 10326003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => FinFET device and methods of forming [patent_app_type] => utility [patent_app_number] => 15/473089 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 8887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15473089 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/473089
FinFET device and methods of forming Mar 28, 2017 Issued
Array ( [id] => 15286753 [patent_doc_number] => 10516047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Structure and formation method of semiconductor device structure [patent_app_type] => utility [patent_app_number] => 15/471318 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15471318 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/471318
Structure and formation method of semiconductor device structure Mar 27, 2017 Issued
Array ( [id] => 16433085 [patent_doc_number] => 10833184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Semiconductor device substrate, semiconductor device, and method for manufacturing semiconductor device substrate [patent_app_type] => utility [patent_app_number] => 16/330884 [patent_app_country] => US [patent_app_date] => 2017-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7228 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16330884 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/330884
Semiconductor device substrate, semiconductor device, and method for manufacturing semiconductor device substrate Feb 23, 2017 Issued
Array ( [id] => 12314823 [patent_doc_number] => 09941327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Detector module for an imaging system [patent_app_type] => utility [patent_app_number] => 15/437628 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 6672 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437628 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/437628
Detector module for an imaging system Feb 20, 2017 Issued
Array ( [id] => 15315865 [patent_doc_number] => 10522650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Semiconductor device and methods of manufacture [patent_app_type] => utility [patent_app_number] => 15/433121 [patent_app_country] => US [patent_app_date] => 2017-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15433121 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/433121
Semiconductor device and methods of manufacture Feb 14, 2017 Issued
Array ( [id] => 13364081 [patent_doc_number] => 20180233580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => SEMICONDUCTOR STRUCTURE WITH GATE HEIGHT SCALING [patent_app_type] => utility [patent_app_number] => 15/432710 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432710 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432710
SEMICONDUCTOR STRUCTURE WITH GATE HEIGHT SCALING Feb 13, 2017 Abandoned
Array ( [id] => 13419935 [patent_doc_number] => 20180261510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => TONE INVERSION METHOD AND STRUCTURE FOR SELECTIVE CONTACT VIA PATTERNING [patent_app_type] => utility [patent_app_number] => 15/432016 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432016 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432016
Tone inversion method and structure for selective contact via patterning Feb 13, 2017 Issued
Array ( [id] => 12779188 [patent_doc_number] => 20180151564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH SEPARATED MERGED SOURCE/DRAIN STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/429844 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15429844 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/429844
Method of manufacturing a semiconductor device with separated merged source/drain structure Feb 9, 2017 Issued
Array ( [id] => 14920511 [patent_doc_number] => 10431583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Semiconductor device including transistors with adjusted threshold voltages [patent_app_type] => utility [patent_app_number] => 15/430265 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 79 [patent_figures_cnt] => 85 [patent_no_of_words] => 32203 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15430265 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/430265
Semiconductor device including transistors with adjusted threshold voltages Feb 9, 2017 Issued
Array ( [id] => 16148469 [patent_doc_number] => 10707316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Structure and formation method of semiconductor device structure with gate structure [patent_app_type] => utility [patent_app_number] => 15/429797 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15429797 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/429797
Structure and formation method of semiconductor device structure with gate structure Feb 9, 2017 Issued
Array ( [id] => 13306603 [patent_doc_number] => 20180204838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => INTEGRATED CIRCUIT STRUCTURE WITH SEMICONDUCTOR DEVICES AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/427512 [patent_app_country] => US [patent_app_date] => 2017-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15427512 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/427512
Integrated circuit structure with semiconductor devices and method of fabricating the same Feb 7, 2017 Issued
Array ( [id] => 15760447 [patent_doc_number] => 10622352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Fin cut to prevent replacement gate collapse on STI [patent_app_type] => utility [patent_app_number] => 15/415446 [patent_app_country] => US [patent_app_date] => 2017-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 7394 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15415446 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/415446
Fin cut to prevent replacement gate collapse on STI Jan 24, 2017 Issued
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